1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * MFD core driver for Rockchip RK808/RK818
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2014-2018, Fuzhou Rockchip Electronics Co., Ltd
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Chris Zhong <zyw@rock-chips.com>
8*4882a593Smuzhiyun * Author: Zhang Qing <zhangqing@rock-chips.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Copyright (C) 2016 PHYTEC Messtechnik GmbH
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Author: Wadim Egorov <w.egorov@phytec.de>
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/mfd/rk808.h>
18*4882a593Smuzhiyun #include <linux/mfd/core.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/of_device.h>
21*4882a593Smuzhiyun #include <linux/reboot.h>
22*4882a593Smuzhiyun #include <linux/regmap.h>
23*4882a593Smuzhiyun #include <linux/syscore_ops.h>
24*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
25*4882a593Smuzhiyun #include <linux/pinctrl/devinfo.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct rk808_reg_data {
28*4882a593Smuzhiyun int addr;
29*4882a593Smuzhiyun int mask;
30*4882a593Smuzhiyun int value;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
rk808_is_volatile_reg(struct device * dev,unsigned int reg)33*4882a593Smuzhiyun static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun * Notes:
37*4882a593Smuzhiyun * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but
38*4882a593Smuzhiyun * we don't use that feature. It's better to cache.
39*4882a593Smuzhiyun * - It's unlikely we care that RK808_DEVCTRL_REG is volatile since
40*4882a593Smuzhiyun * bits are cleared in case when we shutoff anyway, but better safe.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun switch (reg) {
44*4882a593Smuzhiyun case RK808_SECONDS_REG ... RK808_WEEKS_REG:
45*4882a593Smuzhiyun case RK808_RTC_STATUS_REG:
46*4882a593Smuzhiyun case RK808_VB_MON_REG:
47*4882a593Smuzhiyun case RK808_THERMAL_REG:
48*4882a593Smuzhiyun case RK808_DCDC_UV_STS_REG:
49*4882a593Smuzhiyun case RK808_LDO_UV_STS_REG:
50*4882a593Smuzhiyun case RK808_DCDC_PG_REG:
51*4882a593Smuzhiyun case RK808_LDO_PG_REG:
52*4882a593Smuzhiyun case RK808_DEVCTRL_REG:
53*4882a593Smuzhiyun case RK808_INT_STS_REG1:
54*4882a593Smuzhiyun case RK808_INT_STS_REG2:
55*4882a593Smuzhiyun return true;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return false;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
rk817_is_volatile_reg(struct device * dev,unsigned int reg)61*4882a593Smuzhiyun static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * Notes:
65*4882a593Smuzhiyun * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but
66*4882a593Smuzhiyun * we don't use that feature. It's better to cache.
67*4882a593Smuzhiyun */
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun switch (reg) {
70*4882a593Smuzhiyun case RK817_SECONDS_REG ... RK817_WEEKS_REG:
71*4882a593Smuzhiyun case RK817_RTC_STATUS_REG:
72*4882a593Smuzhiyun case RK817_ADC_CONFIG0 ... RK817_CURE_ADC_K0:
73*4882a593Smuzhiyun case RK817_CHRG_STS:
74*4882a593Smuzhiyun case RK817_CHRG_OUT:
75*4882a593Smuzhiyun case RK817_CHRG_IN:
76*4882a593Smuzhiyun case RK817_SYS_STS:
77*4882a593Smuzhiyun case RK817_INT_STS_REG0:
78*4882a593Smuzhiyun case RK817_INT_STS_REG1:
79*4882a593Smuzhiyun case RK817_INT_STS_REG2:
80*4882a593Smuzhiyun return true;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return false;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
rk818_is_volatile_reg(struct device * dev,unsigned int reg)86*4882a593Smuzhiyun static bool rk818_is_volatile_reg(struct device *dev, unsigned int reg)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun /*
89*4882a593Smuzhiyun * Notes:
90*4882a593Smuzhiyun * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but
91*4882a593Smuzhiyun * we don't use that feature. It's better to cache.
92*4882a593Smuzhiyun * - It's unlikely we care that RK808_DEVCTRL_REG is volatile since
93*4882a593Smuzhiyun * bits are cleared in case when we shutoff anyway, but better safe.
94*4882a593Smuzhiyun */
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun switch (reg) {
97*4882a593Smuzhiyun case RK808_SECONDS_REG ... RK808_WEEKS_REG:
98*4882a593Smuzhiyun case RK808_RTC_STATUS_REG:
99*4882a593Smuzhiyun case RK808_VB_MON_REG:
100*4882a593Smuzhiyun case RK808_THERMAL_REG:
101*4882a593Smuzhiyun case RK808_DCDC_EN_REG:
102*4882a593Smuzhiyun case RK808_LDO_EN_REG:
103*4882a593Smuzhiyun case RK808_DCDC_UV_STS_REG:
104*4882a593Smuzhiyun case RK808_LDO_UV_STS_REG:
105*4882a593Smuzhiyun case RK808_DCDC_PG_REG:
106*4882a593Smuzhiyun case RK808_LDO_PG_REG:
107*4882a593Smuzhiyun case RK808_DEVCTRL_REG:
108*4882a593Smuzhiyun case RK808_INT_STS_REG1:
109*4882a593Smuzhiyun case RK808_INT_STS_REG2:
110*4882a593Smuzhiyun case RK808_INT_STS_MSK_REG1:
111*4882a593Smuzhiyun case RK808_INT_STS_MSK_REG2:
112*4882a593Smuzhiyun case RK816_INT_STS_REG1:
113*4882a593Smuzhiyun case RK816_INT_STS_MSK_REG1:
114*4882a593Smuzhiyun case RK818_SUP_STS_REG ... RK818_SAVE_DATA19:
115*4882a593Smuzhiyun return true;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun return false;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun static const struct regmap_config rk818_regmap_config = {
122*4882a593Smuzhiyun .reg_bits = 8,
123*4882a593Smuzhiyun .val_bits = 8,
124*4882a593Smuzhiyun .max_register = RK818_SAVE_DATA19,
125*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
126*4882a593Smuzhiyun .volatile_reg = rk818_is_volatile_reg,
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun static const struct regmap_config rk805_regmap_config = {
130*4882a593Smuzhiyun .reg_bits = 8,
131*4882a593Smuzhiyun .val_bits = 8,
132*4882a593Smuzhiyun .max_register = RK805_OFF_SOURCE_REG,
133*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
134*4882a593Smuzhiyun .volatile_reg = rk808_is_volatile_reg,
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun static const struct regmap_config rk808_regmap_config = {
138*4882a593Smuzhiyun .reg_bits = 8,
139*4882a593Smuzhiyun .val_bits = 8,
140*4882a593Smuzhiyun .max_register = RK808_IO_POL_REG,
141*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
142*4882a593Smuzhiyun .volatile_reg = rk808_is_volatile_reg,
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static const struct regmap_config rk816_regmap_config = {
146*4882a593Smuzhiyun .reg_bits = 8,
147*4882a593Smuzhiyun .val_bits = 8,
148*4882a593Smuzhiyun .max_register = RK816_DATA18_REG,
149*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
150*4882a593Smuzhiyun .volatile_reg = rk818_is_volatile_reg,
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun static const struct regmap_config rk817_regmap_config = {
154*4882a593Smuzhiyun .reg_bits = 8,
155*4882a593Smuzhiyun .val_bits = 8,
156*4882a593Smuzhiyun .max_register = RK817_GPIO_INT_CFG,
157*4882a593Smuzhiyun .num_reg_defaults_raw = RK817_GPIO_INT_CFG + 1,
158*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
159*4882a593Smuzhiyun .volatile_reg = rk817_is_volatile_reg,
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun static const struct resource rtc_resources[] = {
163*4882a593Smuzhiyun DEFINE_RES_IRQ(RK808_IRQ_RTC_ALARM),
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun static const struct resource rk816_rtc_resources[] = {
167*4882a593Smuzhiyun DEFINE_RES_IRQ(RK816_IRQ_RTC_ALARM),
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun static const struct resource rk817_rtc_resources[] = {
171*4882a593Smuzhiyun DEFINE_RES_IRQ(RK817_IRQ_RTC_ALARM),
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun static const struct resource rk805_key_resources[] = {
175*4882a593Smuzhiyun DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL),
176*4882a593Smuzhiyun DEFINE_RES_IRQ(RK805_IRQ_PWRON_RISE),
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun static const struct resource rk816_pwrkey_resources[] = {
180*4882a593Smuzhiyun DEFINE_RES_IRQ(RK816_IRQ_PWRON_FALL),
181*4882a593Smuzhiyun DEFINE_RES_IRQ(RK816_IRQ_PWRON_RISE),
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun static const struct resource rk817_pwrkey_resources[] = {
185*4882a593Smuzhiyun DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL),
186*4882a593Smuzhiyun DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE),
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun static const struct mfd_cell rk805s[] = {
190*4882a593Smuzhiyun { .name = "rk808-clkout", },
191*4882a593Smuzhiyun { .name = "rk808-regulator", },
192*4882a593Smuzhiyun { .name = "rk805-pinctrl", },
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun .name = "rk808-rtc",
195*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(rtc_resources),
196*4882a593Smuzhiyun .resources = &rtc_resources[0],
197*4882a593Smuzhiyun },
198*4882a593Smuzhiyun { .name = "rk805-pwrkey",
199*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(rk805_key_resources),
200*4882a593Smuzhiyun .resources = &rk805_key_resources[0],
201*4882a593Smuzhiyun },
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun static const struct mfd_cell rk808s[] = {
205*4882a593Smuzhiyun { .name = "rk808-clkout", },
206*4882a593Smuzhiyun { .name = "rk808-regulator", },
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun .name = "rk808-rtc",
209*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(rtc_resources),
210*4882a593Smuzhiyun .resources = rtc_resources,
211*4882a593Smuzhiyun },
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun static const struct mfd_cell rk816s[] = {
215*4882a593Smuzhiyun { .name = "rk808-clkout", },
216*4882a593Smuzhiyun { .name = "rk808-regulator", },
217*4882a593Smuzhiyun { .name = "rk805-pinctrl", },
218*4882a593Smuzhiyun { .name = "rk816-battery", .of_compatible = "rk816-battery", },
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun .name = "rk805-pwrkey",
221*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(rk816_pwrkey_resources),
222*4882a593Smuzhiyun .resources = &rk816_pwrkey_resources[0],
223*4882a593Smuzhiyun },
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun .name = "rk808-rtc",
226*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(rk816_rtc_resources),
227*4882a593Smuzhiyun .resources = &rk816_rtc_resources[0],
228*4882a593Smuzhiyun },
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun static const struct mfd_cell rk817s[] = {
232*4882a593Smuzhiyun { .name = "rk808-clkout",},
233*4882a593Smuzhiyun { .name = "rk808-regulator",},
234*4882a593Smuzhiyun { .name = "rk817-battery", .of_compatible = "rk817,battery", },
235*4882a593Smuzhiyun { .name = "rk817-charger", .of_compatible = "rk817,charger", },
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun .name = "rk805-pwrkey",
238*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(rk817_pwrkey_resources),
239*4882a593Smuzhiyun .resources = &rk817_pwrkey_resources[0],
240*4882a593Smuzhiyun },
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun .name = "rk808-rtc",
243*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(rk817_rtc_resources),
244*4882a593Smuzhiyun .resources = &rk817_rtc_resources[0],
245*4882a593Smuzhiyun },
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun .name = "rk817-codec",
248*4882a593Smuzhiyun .of_compatible = "rockchip,rk817-codec",
249*4882a593Smuzhiyun },
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun static const struct mfd_cell rk818s[] = {
253*4882a593Smuzhiyun { .name = "rk808-clkout", },
254*4882a593Smuzhiyun { .name = "rk808-regulator", },
255*4882a593Smuzhiyun { .name = "rk818-battery", .of_compatible = "rk818-battery", },
256*4882a593Smuzhiyun { .name = "rk818-charger", },
257*4882a593Smuzhiyun {
258*4882a593Smuzhiyun .name = "rk808-rtc",
259*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(rtc_resources),
260*4882a593Smuzhiyun .resources = rtc_resources,
261*4882a593Smuzhiyun },
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun static const struct rk808_reg_data rk805_pre_init_reg[] = {
265*4882a593Smuzhiyun {RK805_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_400MA},
266*4882a593Smuzhiyun {RK805_GPIO_IO_POL_REG, SLP_SD_MSK, SLEEP_FUN},
267*4882a593Smuzhiyun {RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C},
268*4882a593Smuzhiyun {RK808_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun static struct rk808_reg_data rk805_suspend_reg[] = {
272*4882a593Smuzhiyun {RK805_BUCK3_CONFIG_REG, PWM_MODE_MSK, AUTO_PWM_MODE},
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun static struct rk808_reg_data rk805_resume_reg[] = {
276*4882a593Smuzhiyun {RK805_BUCK3_CONFIG_REG, PWM_MODE_MSK, FPWM_MODE},
277*4882a593Smuzhiyun };
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun static const struct rk808_reg_data rk808_pre_init_reg[] = {
280*4882a593Smuzhiyun { RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_150MA },
281*4882a593Smuzhiyun { RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_200MA },
282*4882a593Smuzhiyun { RK808_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA },
283*4882a593Smuzhiyun { RK808_BUCK1_CONFIG_REG, BUCK1_RATE_MASK, BUCK_ILMIN_200MA },
284*4882a593Smuzhiyun { RK808_BUCK2_CONFIG_REG, BUCK2_RATE_MASK, BUCK_ILMIN_200MA },
285*4882a593Smuzhiyun { RK808_DCDC_UV_ACT_REG, BUCK_UV_ACT_MASK, BUCK_UV_ACT_DISABLE},
286*4882a593Smuzhiyun { RK808_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
287*4882a593Smuzhiyun { RK808_VB_MON_REG, MASK_ALL, VB_LO_ACT |
288*4882a593Smuzhiyun VB_LO_SEL_3500MV },
289*4882a593Smuzhiyun };
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun static const struct rk808_reg_data rk816_pre_init_reg[] = {
292*4882a593Smuzhiyun /* buck4 Max ILMIT*/
293*4882a593Smuzhiyun { RK816_BUCK4_CONFIG_REG, REG_WRITE_MSK, BUCK4_MAX_ILIMIT },
294*4882a593Smuzhiyun /* hotdie temperature: 105c*/
295*4882a593Smuzhiyun { RK816_THERMAL_REG, REG_WRITE_MSK, TEMP105C },
296*4882a593Smuzhiyun /* set buck 12.5mv/us */
297*4882a593Smuzhiyun { RK816_BUCK1_CONFIG_REG, BUCK_RATE_MSK, BUCK_RATE_12_5MV_US },
298*4882a593Smuzhiyun { RK816_BUCK2_CONFIG_REG, BUCK_RATE_MSK, BUCK_RATE_12_5MV_US },
299*4882a593Smuzhiyun /* enable RTC_PERIOD & RTC_ALARM int */
300*4882a593Smuzhiyun { RK816_INT_STS_MSK_REG2, REG_WRITE_MSK, RTC_PERIOD_ALARM_INT_EN },
301*4882a593Smuzhiyun /* set bat 3.0 low and act shutdown */
302*4882a593Smuzhiyun { RK816_VB_MON_REG, VBAT_LOW_VOL_MASK | VBAT_LOW_ACT_MASK,
303*4882a593Smuzhiyun RK816_VBAT_LOW_3V0 | EN_VABT_LOW_SHUT_DOWN },
304*4882a593Smuzhiyun /* enable PWRON rising/faling int */
305*4882a593Smuzhiyun { RK816_INT_STS_MSK_REG1, REG_WRITE_MSK, RK816_PWRON_FALL_RISE_INT_EN },
306*4882a593Smuzhiyun /* enable PLUG IN/OUT int */
307*4882a593Smuzhiyun { RK816_INT_STS_MSK_REG3, REG_WRITE_MSK, PLUGIN_OUT_INT_EN },
308*4882a593Smuzhiyun /* clear int flags */
309*4882a593Smuzhiyun { RK816_INT_STS_REG1, REG_WRITE_MSK, ALL_INT_FLAGS_ST },
310*4882a593Smuzhiyun { RK816_INT_STS_REG2, REG_WRITE_MSK, ALL_INT_FLAGS_ST },
311*4882a593Smuzhiyun { RK816_INT_STS_REG3, REG_WRITE_MSK, ALL_INT_FLAGS_ST },
312*4882a593Smuzhiyun { RK816_DCDC_EN_REG2, BOOST_EN_MASK, BOOST_DISABLE },
313*4882a593Smuzhiyun /* set write mask bit 1, otherwise 'is_enabled()' get wrong status */
314*4882a593Smuzhiyun { RK816_LDO_EN_REG1, REGS_WMSK, REGS_WMSK },
315*4882a593Smuzhiyun { RK816_LDO_EN_REG2, REGS_WMSK, REGS_WMSK },
316*4882a593Smuzhiyun };
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun static const struct rk808_reg_data rk817_pre_init_reg[] = {
319*4882a593Smuzhiyun {RK817_SYS_CFG(3), RK817_SLPPOL_MSK, RK817_SLPPOL_L},
320*4882a593Smuzhiyun {RK817_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
321*4882a593Smuzhiyun {RK817_GPIO_INT_CFG, RK817_INT_POL_MSK, RK817_INT_POL_L},
322*4882a593Smuzhiyun {RK817_SYS_CFG(1), RK817_HOTDIE_TEMP_MSK | RK817_TSD_TEMP_MSK,
323*4882a593Smuzhiyun RK817_HOTDIE_105 | RK817_TSD_140},
324*4882a593Smuzhiyun };
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun static const struct rk808_reg_data rk818_pre_init_reg[] = {
327*4882a593Smuzhiyun /* improve efficiency */
328*4882a593Smuzhiyun { RK818_BUCK2_CONFIG_REG, BUCK2_RATE_MASK, BUCK_ILMIN_250MA },
329*4882a593Smuzhiyun { RK818_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_250MA },
330*4882a593Smuzhiyun { RK818_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA },
331*4882a593Smuzhiyun { RK818_USB_CTRL_REG, RK818_USB_ILIM_SEL_MASK,
332*4882a593Smuzhiyun RK818_USB_ILMIN_2000MA },
333*4882a593Smuzhiyun /* close charger when usb lower then 3.4V */
334*4882a593Smuzhiyun { RK818_USB_CTRL_REG, RK818_USB_CHG_SD_VSEL_MASK,
335*4882a593Smuzhiyun (0x7 << 4) },
336*4882a593Smuzhiyun /* no action when vref */
337*4882a593Smuzhiyun { RK818_H5V_EN_REG, BIT(1), RK818_REF_RDY_CTRL },
338*4882a593Smuzhiyun /* enable HDMI 5V */
339*4882a593Smuzhiyun { RK818_H5V_EN_REG, BIT(0), RK818_H5V_EN },
340*4882a593Smuzhiyun { RK808_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
341*4882a593Smuzhiyun { RK808_VB_MON_REG, MASK_ALL, VB_LO_ACT |
342*4882a593Smuzhiyun VB_LO_SEL_3500MV },
343*4882a593Smuzhiyun {RK808_CLK32OUT_REG, CLK32KOUT2_FUNC_MASK, CLK32KOUT2_FUNC},
344*4882a593Smuzhiyun };
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun static const struct regmap_irq rk805_irqs[] = {
347*4882a593Smuzhiyun [RK805_IRQ_PWRON_RISE] = {
348*4882a593Smuzhiyun .mask = RK805_IRQ_PWRON_RISE_MSK,
349*4882a593Smuzhiyun .reg_offset = 0,
350*4882a593Smuzhiyun },
351*4882a593Smuzhiyun [RK805_IRQ_VB_LOW] = {
352*4882a593Smuzhiyun .mask = RK805_IRQ_VB_LOW_MSK,
353*4882a593Smuzhiyun .reg_offset = 0,
354*4882a593Smuzhiyun },
355*4882a593Smuzhiyun [RK805_IRQ_PWRON] = {
356*4882a593Smuzhiyun .mask = RK805_IRQ_PWRON_MSK,
357*4882a593Smuzhiyun .reg_offset = 0,
358*4882a593Smuzhiyun },
359*4882a593Smuzhiyun [RK805_IRQ_PWRON_LP] = {
360*4882a593Smuzhiyun .mask = RK805_IRQ_PWRON_LP_MSK,
361*4882a593Smuzhiyun .reg_offset = 0,
362*4882a593Smuzhiyun },
363*4882a593Smuzhiyun [RK805_IRQ_HOTDIE] = {
364*4882a593Smuzhiyun .mask = RK805_IRQ_HOTDIE_MSK,
365*4882a593Smuzhiyun .reg_offset = 0,
366*4882a593Smuzhiyun },
367*4882a593Smuzhiyun [RK805_IRQ_RTC_ALARM] = {
368*4882a593Smuzhiyun .mask = RK805_IRQ_RTC_ALARM_MSK,
369*4882a593Smuzhiyun .reg_offset = 0,
370*4882a593Smuzhiyun },
371*4882a593Smuzhiyun [RK805_IRQ_RTC_PERIOD] = {
372*4882a593Smuzhiyun .mask = RK805_IRQ_RTC_PERIOD_MSK,
373*4882a593Smuzhiyun .reg_offset = 0,
374*4882a593Smuzhiyun },
375*4882a593Smuzhiyun [RK805_IRQ_PWRON_FALL] = {
376*4882a593Smuzhiyun .mask = RK805_IRQ_PWRON_FALL_MSK,
377*4882a593Smuzhiyun .reg_offset = 0,
378*4882a593Smuzhiyun },
379*4882a593Smuzhiyun };
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun static const struct regmap_irq rk808_irqs[] = {
382*4882a593Smuzhiyun /* INT_STS */
383*4882a593Smuzhiyun [RK808_IRQ_VOUT_LO] = {
384*4882a593Smuzhiyun .mask = RK808_IRQ_VOUT_LO_MSK,
385*4882a593Smuzhiyun .reg_offset = 0,
386*4882a593Smuzhiyun },
387*4882a593Smuzhiyun [RK808_IRQ_VB_LO] = {
388*4882a593Smuzhiyun .mask = RK808_IRQ_VB_LO_MSK,
389*4882a593Smuzhiyun .reg_offset = 0,
390*4882a593Smuzhiyun },
391*4882a593Smuzhiyun [RK808_IRQ_PWRON] = {
392*4882a593Smuzhiyun .mask = RK808_IRQ_PWRON_MSK,
393*4882a593Smuzhiyun .reg_offset = 0,
394*4882a593Smuzhiyun },
395*4882a593Smuzhiyun [RK808_IRQ_PWRON_LP] = {
396*4882a593Smuzhiyun .mask = RK808_IRQ_PWRON_LP_MSK,
397*4882a593Smuzhiyun .reg_offset = 0,
398*4882a593Smuzhiyun },
399*4882a593Smuzhiyun [RK808_IRQ_HOTDIE] = {
400*4882a593Smuzhiyun .mask = RK808_IRQ_HOTDIE_MSK,
401*4882a593Smuzhiyun .reg_offset = 0,
402*4882a593Smuzhiyun },
403*4882a593Smuzhiyun [RK808_IRQ_RTC_ALARM] = {
404*4882a593Smuzhiyun .mask = RK808_IRQ_RTC_ALARM_MSK,
405*4882a593Smuzhiyun .reg_offset = 0,
406*4882a593Smuzhiyun },
407*4882a593Smuzhiyun [RK808_IRQ_RTC_PERIOD] = {
408*4882a593Smuzhiyun .mask = RK808_IRQ_RTC_PERIOD_MSK,
409*4882a593Smuzhiyun .reg_offset = 0,
410*4882a593Smuzhiyun },
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun /* INT_STS2 */
413*4882a593Smuzhiyun [RK808_IRQ_PLUG_IN_INT] = {
414*4882a593Smuzhiyun .mask = RK808_IRQ_PLUG_IN_INT_MSK,
415*4882a593Smuzhiyun .reg_offset = 1,
416*4882a593Smuzhiyun },
417*4882a593Smuzhiyun [RK808_IRQ_PLUG_OUT_INT] = {
418*4882a593Smuzhiyun .mask = RK808_IRQ_PLUG_OUT_INT_MSK,
419*4882a593Smuzhiyun .reg_offset = 1,
420*4882a593Smuzhiyun },
421*4882a593Smuzhiyun };
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun static struct rk808_reg_data rk816_suspend_reg[] = {
424*4882a593Smuzhiyun /* set bat 3.4v low and act irq */
425*4882a593Smuzhiyun { RK816_VB_MON_REG, VBAT_LOW_VOL_MASK | VBAT_LOW_ACT_MASK,
426*4882a593Smuzhiyun RK816_VBAT_LOW_3V4 | EN_VBAT_LOW_IRQ },
427*4882a593Smuzhiyun };
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun static struct rk808_reg_data rk816_resume_reg[] = {
430*4882a593Smuzhiyun /* set bat 3.0v low and act shutdown */
431*4882a593Smuzhiyun { RK816_VB_MON_REG, VBAT_LOW_VOL_MASK | VBAT_LOW_ACT_MASK,
432*4882a593Smuzhiyun RK816_VBAT_LOW_3V0 | EN_VABT_LOW_SHUT_DOWN },
433*4882a593Smuzhiyun };
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun static const struct regmap_irq rk816_irqs[] = {
436*4882a593Smuzhiyun /* INT_STS */
437*4882a593Smuzhiyun [RK816_IRQ_PWRON_FALL] = {
438*4882a593Smuzhiyun .mask = RK816_IRQ_PWRON_FALL_MSK,
439*4882a593Smuzhiyun .reg_offset = 0,
440*4882a593Smuzhiyun },
441*4882a593Smuzhiyun [RK816_IRQ_PWRON_RISE] = {
442*4882a593Smuzhiyun .mask = RK816_IRQ_PWRON_RISE_MSK,
443*4882a593Smuzhiyun .reg_offset = 0,
444*4882a593Smuzhiyun },
445*4882a593Smuzhiyun [RK816_IRQ_VB_LOW] = {
446*4882a593Smuzhiyun .mask = RK816_IRQ_VB_LOW_MSK,
447*4882a593Smuzhiyun .reg_offset = 1,
448*4882a593Smuzhiyun },
449*4882a593Smuzhiyun [RK816_IRQ_PWRON] = {
450*4882a593Smuzhiyun .mask = RK816_IRQ_PWRON_MSK,
451*4882a593Smuzhiyun .reg_offset = 1,
452*4882a593Smuzhiyun },
453*4882a593Smuzhiyun [RK816_IRQ_PWRON_LP] = {
454*4882a593Smuzhiyun .mask = RK816_IRQ_PWRON_LP_MSK,
455*4882a593Smuzhiyun .reg_offset = 1,
456*4882a593Smuzhiyun },
457*4882a593Smuzhiyun [RK816_IRQ_HOTDIE] = {
458*4882a593Smuzhiyun .mask = RK816_IRQ_HOTDIE_MSK,
459*4882a593Smuzhiyun .reg_offset = 1,
460*4882a593Smuzhiyun },
461*4882a593Smuzhiyun [RK816_IRQ_RTC_ALARM] = {
462*4882a593Smuzhiyun .mask = RK816_IRQ_RTC_ALARM_MSK,
463*4882a593Smuzhiyun .reg_offset = 1,
464*4882a593Smuzhiyun },
465*4882a593Smuzhiyun [RK816_IRQ_RTC_PERIOD] = {
466*4882a593Smuzhiyun .mask = RK816_IRQ_RTC_PERIOD_MSK,
467*4882a593Smuzhiyun .reg_offset = 1,
468*4882a593Smuzhiyun },
469*4882a593Smuzhiyun [RK816_IRQ_USB_OV] = {
470*4882a593Smuzhiyun .mask = RK816_IRQ_USB_OV_MSK,
471*4882a593Smuzhiyun .reg_offset = 1,
472*4882a593Smuzhiyun },
473*4882a593Smuzhiyun };
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun static struct rk808_reg_data rk818_suspend_reg[] = {
476*4882a593Smuzhiyun /* set bat 3.4v low and act irq */
477*4882a593Smuzhiyun { RK808_VB_MON_REG, VBAT_LOW_VOL_MASK | VBAT_LOW_ACT_MASK,
478*4882a593Smuzhiyun RK808_VBAT_LOW_3V4 | EN_VBAT_LOW_IRQ },
479*4882a593Smuzhiyun };
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun static struct rk808_reg_data rk818_resume_reg[] = {
482*4882a593Smuzhiyun /* set bat 3.0v low and act shutdown */
483*4882a593Smuzhiyun { RK808_VB_MON_REG, VBAT_LOW_VOL_MASK | VBAT_LOW_ACT_MASK,
484*4882a593Smuzhiyun RK808_VBAT_LOW_3V0 | EN_VABT_LOW_SHUT_DOWN },
485*4882a593Smuzhiyun };
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun static const struct regmap_irq rk818_irqs[] = {
488*4882a593Smuzhiyun /* INT_STS */
489*4882a593Smuzhiyun [RK818_IRQ_VOUT_LO] = {
490*4882a593Smuzhiyun .mask = RK818_IRQ_VOUT_LO_MSK,
491*4882a593Smuzhiyun .reg_offset = 0,
492*4882a593Smuzhiyun },
493*4882a593Smuzhiyun [RK818_IRQ_VB_LO] = {
494*4882a593Smuzhiyun .mask = RK818_IRQ_VB_LO_MSK,
495*4882a593Smuzhiyun .reg_offset = 0,
496*4882a593Smuzhiyun },
497*4882a593Smuzhiyun [RK818_IRQ_PWRON] = {
498*4882a593Smuzhiyun .mask = RK818_IRQ_PWRON_MSK,
499*4882a593Smuzhiyun .reg_offset = 0,
500*4882a593Smuzhiyun },
501*4882a593Smuzhiyun [RK818_IRQ_PWRON_LP] = {
502*4882a593Smuzhiyun .mask = RK818_IRQ_PWRON_LP_MSK,
503*4882a593Smuzhiyun .reg_offset = 0,
504*4882a593Smuzhiyun },
505*4882a593Smuzhiyun [RK818_IRQ_HOTDIE] = {
506*4882a593Smuzhiyun .mask = RK818_IRQ_HOTDIE_MSK,
507*4882a593Smuzhiyun .reg_offset = 0,
508*4882a593Smuzhiyun },
509*4882a593Smuzhiyun [RK818_IRQ_RTC_ALARM] = {
510*4882a593Smuzhiyun .mask = RK818_IRQ_RTC_ALARM_MSK,
511*4882a593Smuzhiyun .reg_offset = 0,
512*4882a593Smuzhiyun },
513*4882a593Smuzhiyun [RK818_IRQ_RTC_PERIOD] = {
514*4882a593Smuzhiyun .mask = RK818_IRQ_RTC_PERIOD_MSK,
515*4882a593Smuzhiyun .reg_offset = 0,
516*4882a593Smuzhiyun },
517*4882a593Smuzhiyun [RK818_IRQ_USB_OV] = {
518*4882a593Smuzhiyun .mask = RK818_IRQ_USB_OV_MSK,
519*4882a593Smuzhiyun .reg_offset = 0,
520*4882a593Smuzhiyun },
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun /* INT_STS2 */
523*4882a593Smuzhiyun [RK818_IRQ_PLUG_IN] = {
524*4882a593Smuzhiyun .mask = RK818_IRQ_PLUG_IN_MSK,
525*4882a593Smuzhiyun .reg_offset = 1,
526*4882a593Smuzhiyun },
527*4882a593Smuzhiyun [RK818_IRQ_PLUG_OUT] = {
528*4882a593Smuzhiyun .mask = RK818_IRQ_PLUG_OUT_MSK,
529*4882a593Smuzhiyun .reg_offset = 1,
530*4882a593Smuzhiyun },
531*4882a593Smuzhiyun [RK818_IRQ_CHG_OK] = {
532*4882a593Smuzhiyun .mask = RK818_IRQ_CHG_OK_MSK,
533*4882a593Smuzhiyun .reg_offset = 1,
534*4882a593Smuzhiyun },
535*4882a593Smuzhiyun [RK818_IRQ_CHG_TE] = {
536*4882a593Smuzhiyun .mask = RK818_IRQ_CHG_TE_MSK,
537*4882a593Smuzhiyun .reg_offset = 1,
538*4882a593Smuzhiyun },
539*4882a593Smuzhiyun [RK818_IRQ_CHG_TS1] = {
540*4882a593Smuzhiyun .mask = RK818_IRQ_CHG_TS1_MSK,
541*4882a593Smuzhiyun .reg_offset = 1,
542*4882a593Smuzhiyun },
543*4882a593Smuzhiyun [RK818_IRQ_TS2] = {
544*4882a593Smuzhiyun .mask = RK818_IRQ_TS2_MSK,
545*4882a593Smuzhiyun .reg_offset = 1,
546*4882a593Smuzhiyun },
547*4882a593Smuzhiyun [RK818_IRQ_CHG_CVTLIM] = {
548*4882a593Smuzhiyun .mask = RK818_IRQ_CHG_CVTLIM_MSK,
549*4882a593Smuzhiyun .reg_offset = 1,
550*4882a593Smuzhiyun },
551*4882a593Smuzhiyun [RK818_IRQ_DISCHG_ILIM] = {
552*4882a593Smuzhiyun .mask = RK818_IRQ_DISCHG_ILIM_MSK,
553*4882a593Smuzhiyun .reg_offset = 1,
554*4882a593Smuzhiyun },
555*4882a593Smuzhiyun };
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun static const struct regmap_irq rk817_irqs[RK817_IRQ_END] = {
558*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(0, 8),
559*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(1, 8),
560*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(2, 8),
561*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(3, 8),
562*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(4, 8),
563*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(5, 8),
564*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(6, 8),
565*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(7, 8),
566*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(8, 8),
567*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(9, 8),
568*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(10, 8),
569*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(11, 8),
570*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(12, 8),
571*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(13, 8),
572*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(14, 8),
573*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(15, 8),
574*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(16, 8),
575*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(17, 8),
576*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(18, 8),
577*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(19, 8),
578*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(20, 8),
579*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(21, 8),
580*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(22, 8),
581*4882a593Smuzhiyun REGMAP_IRQ_REG_LINE(23, 8)
582*4882a593Smuzhiyun };
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun static const struct regmap_irq_chip rk805_irq_chip = {
585*4882a593Smuzhiyun .name = "rk805",
586*4882a593Smuzhiyun .irqs = rk805_irqs,
587*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(rk805_irqs),
588*4882a593Smuzhiyun .num_regs = 1,
589*4882a593Smuzhiyun .status_base = RK805_INT_STS_REG,
590*4882a593Smuzhiyun .mask_base = RK805_INT_STS_MSK_REG,
591*4882a593Smuzhiyun .ack_base = RK805_INT_STS_REG,
592*4882a593Smuzhiyun .init_ack_masked = true,
593*4882a593Smuzhiyun };
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun static const struct regmap_irq_chip rk808_irq_chip = {
596*4882a593Smuzhiyun .name = "rk808",
597*4882a593Smuzhiyun .irqs = rk808_irqs,
598*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(rk808_irqs),
599*4882a593Smuzhiyun .num_regs = 2,
600*4882a593Smuzhiyun .irq_reg_stride = 2,
601*4882a593Smuzhiyun .status_base = RK808_INT_STS_REG1,
602*4882a593Smuzhiyun .mask_base = RK808_INT_STS_MSK_REG1,
603*4882a593Smuzhiyun .ack_base = RK808_INT_STS_REG1,
604*4882a593Smuzhiyun .init_ack_masked = true,
605*4882a593Smuzhiyun };
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun static const struct regmap_irq rk816_battery_irqs[] = {
608*4882a593Smuzhiyun /* INT_STS */
609*4882a593Smuzhiyun [RK816_IRQ_PLUG_IN] = {
610*4882a593Smuzhiyun .mask = RK816_IRQ_PLUG_IN_MSK,
611*4882a593Smuzhiyun .reg_offset = 0,
612*4882a593Smuzhiyun },
613*4882a593Smuzhiyun [RK816_IRQ_PLUG_OUT] = {
614*4882a593Smuzhiyun .mask = RK816_IRQ_PLUG_OUT_MSK,
615*4882a593Smuzhiyun .reg_offset = 0,
616*4882a593Smuzhiyun },
617*4882a593Smuzhiyun [RK816_IRQ_CHG_OK] = {
618*4882a593Smuzhiyun .mask = RK816_IRQ_CHG_OK_MSK,
619*4882a593Smuzhiyun .reg_offset = 0,
620*4882a593Smuzhiyun },
621*4882a593Smuzhiyun [RK816_IRQ_CHG_TE] = {
622*4882a593Smuzhiyun .mask = RK816_IRQ_CHG_TE_MSK,
623*4882a593Smuzhiyun .reg_offset = 0,
624*4882a593Smuzhiyun },
625*4882a593Smuzhiyun [RK816_IRQ_CHG_TS] = {
626*4882a593Smuzhiyun .mask = RK816_IRQ_CHG_TS_MSK,
627*4882a593Smuzhiyun .reg_offset = 0,
628*4882a593Smuzhiyun },
629*4882a593Smuzhiyun [RK816_IRQ_CHG_CVTLIM] = {
630*4882a593Smuzhiyun .mask = RK816_IRQ_CHG_CVTLIM_MSK,
631*4882a593Smuzhiyun .reg_offset = 0,
632*4882a593Smuzhiyun },
633*4882a593Smuzhiyun [RK816_IRQ_DISCHG_ILIM] = {
634*4882a593Smuzhiyun .mask = RK816_IRQ_DISCHG_ILIM_MSK,
635*4882a593Smuzhiyun .reg_offset = 0,
636*4882a593Smuzhiyun },
637*4882a593Smuzhiyun };
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun static const struct regmap_irq_chip rk816_irq_chip = {
640*4882a593Smuzhiyun .name = "rk816",
641*4882a593Smuzhiyun .irqs = rk816_irqs,
642*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(rk816_irqs),
643*4882a593Smuzhiyun .num_regs = 2,
644*4882a593Smuzhiyun .irq_reg_stride = 3,
645*4882a593Smuzhiyun .status_base = RK816_INT_STS_REG1,
646*4882a593Smuzhiyun .mask_base = RK816_INT_STS_MSK_REG1,
647*4882a593Smuzhiyun .ack_base = RK816_INT_STS_REG1,
648*4882a593Smuzhiyun .init_ack_masked = true,
649*4882a593Smuzhiyun };
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun static const struct regmap_irq_chip rk816_battery_irq_chip = {
652*4882a593Smuzhiyun .name = "rk816_battery",
653*4882a593Smuzhiyun .irqs = rk816_battery_irqs,
654*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(rk816_battery_irqs),
655*4882a593Smuzhiyun .num_regs = 1,
656*4882a593Smuzhiyun .status_base = RK816_INT_STS_REG3,
657*4882a593Smuzhiyun .mask_base = RK816_INT_STS_MSK_REG3,
658*4882a593Smuzhiyun .ack_base = RK816_INT_STS_REG3,
659*4882a593Smuzhiyun .init_ack_masked = true,
660*4882a593Smuzhiyun };
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun static const struct regmap_irq_chip rk817_irq_chip = {
663*4882a593Smuzhiyun .name = "rk817",
664*4882a593Smuzhiyun .irqs = rk817_irqs,
665*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(rk817_irqs),
666*4882a593Smuzhiyun .num_regs = 3,
667*4882a593Smuzhiyun .irq_reg_stride = 2,
668*4882a593Smuzhiyun .status_base = RK817_INT_STS_REG0,
669*4882a593Smuzhiyun .mask_base = RK817_INT_STS_MSK_REG0,
670*4882a593Smuzhiyun .ack_base = RK817_INT_STS_REG0,
671*4882a593Smuzhiyun .init_ack_masked = true,
672*4882a593Smuzhiyun };
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun static const struct regmap_irq_chip rk818_irq_chip = {
675*4882a593Smuzhiyun .name = "rk818",
676*4882a593Smuzhiyun .irqs = rk818_irqs,
677*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(rk818_irqs),
678*4882a593Smuzhiyun .num_regs = 2,
679*4882a593Smuzhiyun .irq_reg_stride = 2,
680*4882a593Smuzhiyun .status_base = RK818_INT_STS_REG1,
681*4882a593Smuzhiyun .mask_base = RK818_INT_STS_MSK_REG1,
682*4882a593Smuzhiyun .ack_base = RK818_INT_STS_REG1,
683*4882a593Smuzhiyun .init_ack_masked = true,
684*4882a593Smuzhiyun };
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun static struct i2c_client *rk808_i2c_client;
687*4882a593Smuzhiyun static struct rk808_reg_data *suspend_reg, *resume_reg;
688*4882a593Smuzhiyun static int suspend_reg_num, resume_reg_num;
689*4882a593Smuzhiyun
rk805_device_shutdown_prepare(void)690*4882a593Smuzhiyun static void rk805_device_shutdown_prepare(void)
691*4882a593Smuzhiyun {
692*4882a593Smuzhiyun int ret;
693*4882a593Smuzhiyun struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun if (!rk808)
696*4882a593Smuzhiyun return;
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap,
699*4882a593Smuzhiyun RK805_GPIO_IO_POL_REG,
700*4882a593Smuzhiyun SLP_SD_MSK, SHUTDOWN_FUN);
701*4882a593Smuzhiyun if (ret)
702*4882a593Smuzhiyun dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n");
703*4882a593Smuzhiyun }
704*4882a593Smuzhiyun
rk817_shutdown_prepare(void)705*4882a593Smuzhiyun static void rk817_shutdown_prepare(void)
706*4882a593Smuzhiyun {
707*4882a593Smuzhiyun int ret;
708*4882a593Smuzhiyun struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun /* close rtc int when power off */
711*4882a593Smuzhiyun regmap_update_bits(rk808->regmap,
712*4882a593Smuzhiyun RK817_INT_STS_MSK_REG0,
713*4882a593Smuzhiyun (0x3 << 5), (0x3 << 5));
714*4882a593Smuzhiyun regmap_update_bits(rk808->regmap,
715*4882a593Smuzhiyun RK817_RTC_INT_REG,
716*4882a593Smuzhiyun (0x3 << 2), (0x0 << 2));
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun if (rk808->pins && rk808->pins->p && rk808->pins->power_off) {
719*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap,
720*4882a593Smuzhiyun RK817_SYS_CFG(3),
721*4882a593Smuzhiyun RK817_SLPPIN_FUNC_MSK,
722*4882a593Smuzhiyun SLPPIN_NULL_FUN);
723*4882a593Smuzhiyun if (ret)
724*4882a593Smuzhiyun pr_err("shutdown: config SLPPIN_NULL_FUN error!\n");
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap,
727*4882a593Smuzhiyun RK817_SYS_CFG(3),
728*4882a593Smuzhiyun RK817_SLPPOL_MSK,
729*4882a593Smuzhiyun RK817_SLPPOL_H);
730*4882a593Smuzhiyun if (ret)
731*4882a593Smuzhiyun pr_err("shutdown: config RK817_SLPPOL_H error!\n");
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun ret = pinctrl_select_state(rk808->pins->p,
734*4882a593Smuzhiyun rk808->pins->power_off);
735*4882a593Smuzhiyun if (ret)
736*4882a593Smuzhiyun pr_info("%s:failed to activate pwroff state\n",
737*4882a593Smuzhiyun __func__);
738*4882a593Smuzhiyun }
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun /* pmic sleep shutdown function */
741*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap,
742*4882a593Smuzhiyun RK817_SYS_CFG(3),
743*4882a593Smuzhiyun RK817_SLPPIN_FUNC_MSK, SLPPIN_DN_FUN);
744*4882a593Smuzhiyun if (ret)
745*4882a593Smuzhiyun dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n");
746*4882a593Smuzhiyun /* pmic need the SCL clock to synchronize register */
747*4882a593Smuzhiyun mdelay(2);
748*4882a593Smuzhiyun }
749*4882a593Smuzhiyun
rk8xx_device_shutdown(void)750*4882a593Smuzhiyun static void rk8xx_device_shutdown(void)
751*4882a593Smuzhiyun {
752*4882a593Smuzhiyun int ret;
753*4882a593Smuzhiyun unsigned int reg, bit;
754*4882a593Smuzhiyun struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun switch (rk808->variant) {
757*4882a593Smuzhiyun case RK805_ID:
758*4882a593Smuzhiyun reg = RK805_DEV_CTRL_REG;
759*4882a593Smuzhiyun bit = DEV_OFF;
760*4882a593Smuzhiyun break;
761*4882a593Smuzhiyun case RK808_ID:
762*4882a593Smuzhiyun reg = RK808_DEVCTRL_REG,
763*4882a593Smuzhiyun bit = DEV_OFF_RST;
764*4882a593Smuzhiyun break;
765*4882a593Smuzhiyun case RK816_ID:
766*4882a593Smuzhiyun reg = RK816_DEV_CTRL_REG;
767*4882a593Smuzhiyun bit = DEV_OFF;
768*4882a593Smuzhiyun break;
769*4882a593Smuzhiyun case RK818_ID:
770*4882a593Smuzhiyun reg = RK818_DEVCTRL_REG;
771*4882a593Smuzhiyun bit = DEV_OFF;
772*4882a593Smuzhiyun break;
773*4882a593Smuzhiyun default:
774*4882a593Smuzhiyun return;
775*4882a593Smuzhiyun }
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
778*4882a593Smuzhiyun if (ret)
779*4882a593Smuzhiyun dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n");
780*4882a593Smuzhiyun }
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun /* Called in syscore shutdown */
783*4882a593Smuzhiyun static void (*pm_shutdown)(void);
784*4882a593Smuzhiyun
rk8xx_syscore_shutdown(void)785*4882a593Smuzhiyun static void rk8xx_syscore_shutdown(void)
786*4882a593Smuzhiyun {
787*4882a593Smuzhiyun int ret;
788*4882a593Smuzhiyun struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun if (!rk808) {
791*4882a593Smuzhiyun dev_warn(&rk808_i2c_client->dev,
792*4882a593Smuzhiyun "have no rk808, so do nothing here\n");
793*4882a593Smuzhiyun return;
794*4882a593Smuzhiyun }
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun /* close rtc int when power off */
797*4882a593Smuzhiyun regmap_update_bits(rk808->regmap,
798*4882a593Smuzhiyun RK808_INT_STS_MSK_REG1,
799*4882a593Smuzhiyun (0x3 << 5), (0x3 << 5));
800*4882a593Smuzhiyun regmap_update_bits(rk808->regmap,
801*4882a593Smuzhiyun RK808_RTC_INT_REG,
802*4882a593Smuzhiyun (0x3 << 2), (0x0 << 2));
803*4882a593Smuzhiyun /*
804*4882a593Smuzhiyun * For PMIC that power off supplies by write register via i2c bus,
805*4882a593Smuzhiyun * it's better to do power off at syscore shutdown here.
806*4882a593Smuzhiyun *
807*4882a593Smuzhiyun * Because when run to kernel's "pm_power_off" call, i2c may has
808*4882a593Smuzhiyun * been stopped or PMIC may not be able to get i2c transfer while
809*4882a593Smuzhiyun * there are too many devices are competiting.
810*4882a593Smuzhiyun */
811*4882a593Smuzhiyun if (system_state == SYSTEM_POWER_OFF) {
812*4882a593Smuzhiyun if (rk808->variant == RK809_ID || rk808->variant == RK817_ID) {
813*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap,
814*4882a593Smuzhiyun RK817_SYS_CFG(3),
815*4882a593Smuzhiyun RK817_SLPPIN_FUNC_MSK,
816*4882a593Smuzhiyun SLPPIN_DN_FUN);
817*4882a593Smuzhiyun if (ret) {
818*4882a593Smuzhiyun dev_warn(&rk808_i2c_client->dev,
819*4882a593Smuzhiyun "Cannot switch to power down function\n");
820*4882a593Smuzhiyun }
821*4882a593Smuzhiyun }
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun if (pm_shutdown) {
824*4882a593Smuzhiyun dev_info(&rk808_i2c_client->dev, "System power off\n");
825*4882a593Smuzhiyun pm_shutdown();
826*4882a593Smuzhiyun mdelay(10);
827*4882a593Smuzhiyun dev_info(&rk808_i2c_client->dev,
828*4882a593Smuzhiyun "Power off failed !\n");
829*4882a593Smuzhiyun while (1)
830*4882a593Smuzhiyun ;
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun }
833*4882a593Smuzhiyun }
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun static struct syscore_ops rk808_syscore_ops = {
836*4882a593Smuzhiyun .shutdown = rk8xx_syscore_shutdown,
837*4882a593Smuzhiyun };
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun /*
840*4882a593Smuzhiyun * RK8xx PMICs would do real power off in syscore shutdown, if "pm_power_off"
841*4882a593Smuzhiyun * is not assigned(e.g. PSCI is not enabled), we have to provide a dummy
842*4882a593Smuzhiyun * callback for it, otherwise there comes a halt in Reboot system call:
843*4882a593Smuzhiyun *
844*4882a593Smuzhiyun * if ((cmd == LINUX_REBOOT_CMD_POWER_OFF) && !pm_power_off)
845*4882a593Smuzhiyun * cmd = LINUX_REBOOT_CMD_HALT;
846*4882a593Smuzhiyun */
rk808_pm_power_off_dummy(void)847*4882a593Smuzhiyun static void rk808_pm_power_off_dummy(void)
848*4882a593Smuzhiyun {
849*4882a593Smuzhiyun pr_info("Dummy power off for RK8xx PMICs, should never reach here!\n");
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun while (1)
852*4882a593Smuzhiyun ;
853*4882a593Smuzhiyun }
854*4882a593Smuzhiyun
rk8xx_dbg_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)855*4882a593Smuzhiyun static ssize_t rk8xx_dbg_store(struct device *dev,
856*4882a593Smuzhiyun struct device_attribute *attr,
857*4882a593Smuzhiyun const char *buf, size_t count)
858*4882a593Smuzhiyun {
859*4882a593Smuzhiyun int ret;
860*4882a593Smuzhiyun char cmd;
861*4882a593Smuzhiyun u32 input[2], addr, data;
862*4882a593Smuzhiyun struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun ret = sscanf(buf, "%c ", &cmd);
865*4882a593Smuzhiyun if (ret != 1) {
866*4882a593Smuzhiyun pr_err("Unknown command\n");
867*4882a593Smuzhiyun goto out;
868*4882a593Smuzhiyun }
869*4882a593Smuzhiyun switch (cmd) {
870*4882a593Smuzhiyun case 'w':
871*4882a593Smuzhiyun ret = sscanf(buf, "%c %x %x ", &cmd, &input[0], &input[1]);
872*4882a593Smuzhiyun if (ret != 3) {
873*4882a593Smuzhiyun pr_err("error! cmd format: echo w [addr] [value]\n");
874*4882a593Smuzhiyun goto out;
875*4882a593Smuzhiyun };
876*4882a593Smuzhiyun addr = input[0] & 0xff;
877*4882a593Smuzhiyun data = input[1] & 0xff;
878*4882a593Smuzhiyun pr_info("cmd : %c %x %x\n\n", cmd, input[0], input[1]);
879*4882a593Smuzhiyun regmap_write(rk808->regmap, addr, data);
880*4882a593Smuzhiyun regmap_read(rk808->regmap, addr, &data);
881*4882a593Smuzhiyun pr_info("new: %x %x\n", addr, data);
882*4882a593Smuzhiyun break;
883*4882a593Smuzhiyun case 'r':
884*4882a593Smuzhiyun ret = sscanf(buf, "%c %x ", &cmd, &input[0]);
885*4882a593Smuzhiyun if (ret != 2) {
886*4882a593Smuzhiyun pr_err("error! cmd format: echo r [addr]\n");
887*4882a593Smuzhiyun goto out;
888*4882a593Smuzhiyun };
889*4882a593Smuzhiyun pr_info("cmd : %c %x\n\n", cmd, input[0]);
890*4882a593Smuzhiyun addr = input[0] & 0xff;
891*4882a593Smuzhiyun regmap_read(rk808->regmap, addr, &data);
892*4882a593Smuzhiyun pr_info("%x %x\n", input[0], data);
893*4882a593Smuzhiyun break;
894*4882a593Smuzhiyun default:
895*4882a593Smuzhiyun pr_err("Unknown command\n");
896*4882a593Smuzhiyun break;
897*4882a593Smuzhiyun }
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun out:
900*4882a593Smuzhiyun return count;
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun
rk817_pinctrl_init(struct device * dev,struct rk808 * rk808)903*4882a593Smuzhiyun static int rk817_pinctrl_init(struct device *dev, struct rk808 *rk808)
904*4882a593Smuzhiyun {
905*4882a593Smuzhiyun int ret;
906*4882a593Smuzhiyun struct platform_device *pinctrl_dev;
907*4882a593Smuzhiyun struct pinctrl_state *default_st;
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun pinctrl_dev = platform_device_alloc("rk805-pinctrl", -1);
910*4882a593Smuzhiyun if (!pinctrl_dev) {
911*4882a593Smuzhiyun dev_err(dev, "Alloc pinctrl dev failed!\n");
912*4882a593Smuzhiyun return -ENOMEM;
913*4882a593Smuzhiyun }
914*4882a593Smuzhiyun
915*4882a593Smuzhiyun pinctrl_dev->dev.parent = dev;
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun ret = platform_device_add(pinctrl_dev);
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun if (ret) {
920*4882a593Smuzhiyun platform_device_put(pinctrl_dev);
921*4882a593Smuzhiyun dev_err(dev, "Add rk805-pinctrl dev failed!\n");
922*4882a593Smuzhiyun return ret;
923*4882a593Smuzhiyun }
924*4882a593Smuzhiyun if (dev->pins && !IS_ERR(dev->pins->p)) {
925*4882a593Smuzhiyun dev_info(dev, "had get a pinctrl!\n");
926*4882a593Smuzhiyun return 0;
927*4882a593Smuzhiyun }
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun rk808->pins = devm_kzalloc(dev, sizeof(struct rk808_pin_info),
930*4882a593Smuzhiyun GFP_KERNEL);
931*4882a593Smuzhiyun if (!rk808->pins)
932*4882a593Smuzhiyun return -ENOMEM;
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun rk808->pins->p = devm_pinctrl_get(dev);
935*4882a593Smuzhiyun if (IS_ERR(rk808->pins->p)) {
936*4882a593Smuzhiyun rk808->pins->p = NULL;
937*4882a593Smuzhiyun dev_err(dev, "no pinctrl handle\n");
938*4882a593Smuzhiyun return 0;
939*4882a593Smuzhiyun }
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun default_st = pinctrl_lookup_state(rk808->pins->p,
942*4882a593Smuzhiyun PINCTRL_STATE_DEFAULT);
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun if (IS_ERR(default_st)) {
945*4882a593Smuzhiyun dev_dbg(dev, "no default pinctrl state\n");
946*4882a593Smuzhiyun return -EINVAL;
947*4882a593Smuzhiyun }
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun ret = pinctrl_select_state(rk808->pins->p, default_st);
950*4882a593Smuzhiyun if (ret) {
951*4882a593Smuzhiyun dev_dbg(dev, "failed to activate default pinctrl state\n");
952*4882a593Smuzhiyun return -EINVAL;
953*4882a593Smuzhiyun }
954*4882a593Smuzhiyun
955*4882a593Smuzhiyun rk808->pins->power_off = pinctrl_lookup_state(rk808->pins->p,
956*4882a593Smuzhiyun "pmic-power-off");
957*4882a593Smuzhiyun if (IS_ERR(rk808->pins->power_off)) {
958*4882a593Smuzhiyun rk808->pins->power_off = NULL;
959*4882a593Smuzhiyun dev_dbg(dev, "no power-off pinctrl state\n");
960*4882a593Smuzhiyun }
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun rk808->pins->sleep = pinctrl_lookup_state(rk808->pins->p,
963*4882a593Smuzhiyun "pmic-sleep");
964*4882a593Smuzhiyun if (IS_ERR(rk808->pins->sleep)) {
965*4882a593Smuzhiyun rk808->pins->sleep = NULL;
966*4882a593Smuzhiyun dev_dbg(dev, "no sleep-setting state\n");
967*4882a593Smuzhiyun }
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun rk808->pins->reset = pinctrl_lookup_state(rk808->pins->p,
970*4882a593Smuzhiyun "pmic-reset");
971*4882a593Smuzhiyun if (IS_ERR(rk808->pins->reset)) {
972*4882a593Smuzhiyun rk808->pins->reset = NULL;
973*4882a593Smuzhiyun dev_dbg(dev, "no reset-setting pinctrl state\n");
974*4882a593Smuzhiyun return 0;
975*4882a593Smuzhiyun }
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun ret = pinctrl_select_state(rk808->pins->p, rk808->pins->reset);
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun if (ret)
980*4882a593Smuzhiyun dev_dbg(dev, "failed to activate reset-setting pinctrl state\n");
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun return 0;
983*4882a593Smuzhiyun }
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun struct rk817_reboot_data_t {
986*4882a593Smuzhiyun struct rk808 *rk808;
987*4882a593Smuzhiyun struct notifier_block reboot_notifier;
988*4882a593Smuzhiyun };
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun static struct rk817_reboot_data_t rk817_reboot_data;
991*4882a593Smuzhiyun
rk817_reboot_notifier_handler(struct notifier_block * nb,unsigned long action,void * cmd)992*4882a593Smuzhiyun static int rk817_reboot_notifier_handler(struct notifier_block *nb,
993*4882a593Smuzhiyun unsigned long action, void *cmd)
994*4882a593Smuzhiyun {
995*4882a593Smuzhiyun struct rk817_reboot_data_t *data;
996*4882a593Smuzhiyun struct device *dev;
997*4882a593Smuzhiyun int value, power_en_active0, power_en_active1;
998*4882a593Smuzhiyun int ret, i;
999*4882a593Smuzhiyun static const char * const pmic_rst_reg_only_cmd[] = {
1000*4882a593Smuzhiyun "loader", "bootloader", "fastboot", "recovery",
1001*4882a593Smuzhiyun "ums", "panic", "watchdog", "charge",
1002*4882a593Smuzhiyun };
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun data = container_of(nb, struct rk817_reboot_data_t, reboot_notifier);
1005*4882a593Smuzhiyun dev = &data->rk808->i2c->dev;
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun regmap_read(data->rk808->regmap, RK817_POWER_EN_SAVE0,
1008*4882a593Smuzhiyun &power_en_active0);
1009*4882a593Smuzhiyun if (power_en_active0 != 0) {
1010*4882a593Smuzhiyun regmap_read(data->rk808->regmap, RK817_POWER_EN_SAVE1,
1011*4882a593Smuzhiyun &power_en_active1);
1012*4882a593Smuzhiyun value = power_en_active0 & 0x0f;
1013*4882a593Smuzhiyun regmap_write(data->rk808->regmap,
1014*4882a593Smuzhiyun RK817_POWER_EN_REG(0),
1015*4882a593Smuzhiyun value | 0xf0);
1016*4882a593Smuzhiyun value = (power_en_active0 & 0xf0) >> 4;
1017*4882a593Smuzhiyun regmap_write(data->rk808->regmap,
1018*4882a593Smuzhiyun RK817_POWER_EN_REG(1),
1019*4882a593Smuzhiyun value | 0xf0);
1020*4882a593Smuzhiyun value = power_en_active1 & 0x0f;
1021*4882a593Smuzhiyun regmap_write(data->rk808->regmap,
1022*4882a593Smuzhiyun RK817_POWER_EN_REG(2),
1023*4882a593Smuzhiyun value | 0xf0);
1024*4882a593Smuzhiyun value = (power_en_active1 & 0xf0) >> 4;
1025*4882a593Smuzhiyun regmap_write(data->rk808->regmap,
1026*4882a593Smuzhiyun RK817_POWER_EN_REG(3),
1027*4882a593Smuzhiyun value | 0xf0);
1028*4882a593Smuzhiyun } else {
1029*4882a593Smuzhiyun dev_info(dev, "reboot: not restore POWER_EN\n");
1030*4882a593Smuzhiyun }
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun if (action != SYS_RESTART || !cmd)
1033*4882a593Smuzhiyun return NOTIFY_OK;
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun /*
1036*4882a593Smuzhiyun * When system restart, there are two rst actions of PMIC sleep if
1037*4882a593Smuzhiyun * board hardware support:
1038*4882a593Smuzhiyun *
1039*4882a593Smuzhiyun * 0b'00: reset the PMIC itself completely.
1040*4882a593Smuzhiyun * 0b'01: reset the 'RST' related register only.
1041*4882a593Smuzhiyun *
1042*4882a593Smuzhiyun * In the case of 0b'00, PMIC reset itself which triggers SoC NPOR-reset
1043*4882a593Smuzhiyun * at the same time, so the command: reboot load/bootload/recovery, etc
1044*4882a593Smuzhiyun * is not effect any more.
1045*4882a593Smuzhiyun *
1046*4882a593Smuzhiyun * Here we check if this reboot cmd is what we expect for 0b'01.
1047*4882a593Smuzhiyun */
1048*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(pmic_rst_reg_only_cmd); i++) {
1049*4882a593Smuzhiyun if (!strcmp(cmd, pmic_rst_reg_only_cmd[i])) {
1050*4882a593Smuzhiyun ret = regmap_update_bits(data->rk808->regmap,
1051*4882a593Smuzhiyun RK817_SYS_CFG(3),
1052*4882a593Smuzhiyun RK817_RST_FUNC_MSK,
1053*4882a593Smuzhiyun RK817_RST_FUNC_REG);
1054*4882a593Smuzhiyun if (ret)
1055*4882a593Smuzhiyun dev_err(dev, "reboot: force RK817_RST_FUNC_REG error!\n");
1056*4882a593Smuzhiyun else
1057*4882a593Smuzhiyun dev_info(dev, "reboot: force RK817_RST_FUNC_REG ok!\n");
1058*4882a593Smuzhiyun break;
1059*4882a593Smuzhiyun }
1060*4882a593Smuzhiyun }
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun return NOTIFY_OK;
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun
rk817_of_property_prepare(struct rk808 * rk808,struct device * dev)1065*4882a593Smuzhiyun static void rk817_of_property_prepare(struct rk808 *rk808, struct device *dev)
1066*4882a593Smuzhiyun {
1067*4882a593Smuzhiyun u32 inner;
1068*4882a593Smuzhiyun int ret, func, msk, val;
1069*4882a593Smuzhiyun struct device_node *np = dev->of_node;
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun ret = of_property_read_u32_index(np, "fb-inner-reg-idxs", 0, &inner);
1072*4882a593Smuzhiyun if (!ret && inner == RK817_ID_DCDC3)
1073*4882a593Smuzhiyun regmap_update_bits(rk808->regmap, RK817_POWER_CONFIG,
1074*4882a593Smuzhiyun RK817_BUCK3_FB_RES_MSK,
1075*4882a593Smuzhiyun RK817_BUCK3_FB_RES_INTER);
1076*4882a593Smuzhiyun else
1077*4882a593Smuzhiyun regmap_update_bits(rk808->regmap, RK817_POWER_CONFIG,
1078*4882a593Smuzhiyun RK817_BUCK3_FB_RES_MSK,
1079*4882a593Smuzhiyun RK817_BUCK3_FB_RES_EXT);
1080*4882a593Smuzhiyun dev_info(dev, "support dcdc3 fb mode:%d, %d\n", ret, inner);
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun ret = of_property_read_u32(np, "pmic-reset-func", &func);
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun msk = RK817_SLPPIN_FUNC_MSK | RK817_RST_FUNC_MSK;
1085*4882a593Smuzhiyun val = SLPPIN_NULL_FUN;
1086*4882a593Smuzhiyun
1087*4882a593Smuzhiyun if (!ret && func < RK817_RST_FUNC_CNT) {
1088*4882a593Smuzhiyun val |= RK817_RST_FUNC_MSK &
1089*4882a593Smuzhiyun (func << RK817_RST_FUNC_SFT);
1090*4882a593Smuzhiyun } else {
1091*4882a593Smuzhiyun val |= RK817_RST_FUNC_REG;
1092*4882a593Smuzhiyun }
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun regmap_update_bits(rk808->regmap, RK817_SYS_CFG(3), msk, val);
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun dev_info(dev, "support pmic reset mode:%d,%d\n", ret, func);
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun rk817_reboot_data.rk808 = rk808;
1099*4882a593Smuzhiyun rk817_reboot_data.reboot_notifier.notifier_call =
1100*4882a593Smuzhiyun rk817_reboot_notifier_handler;
1101*4882a593Smuzhiyun ret = register_reboot_notifier(&rk817_reboot_data.reboot_notifier);
1102*4882a593Smuzhiyun if (ret)
1103*4882a593Smuzhiyun dev_err(dev, "failed to register reboot nb\n");
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun static struct kobject *rk8xx_kobj;
1107*4882a593Smuzhiyun static struct device_attribute rk8xx_attrs =
1108*4882a593Smuzhiyun __ATTR(rk8xx_dbg, 0200, NULL, rk8xx_dbg_store);
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun static const struct of_device_id rk808_of_match[] = {
1111*4882a593Smuzhiyun { .compatible = "rockchip,rk805" },
1112*4882a593Smuzhiyun { .compatible = "rockchip,rk808" },
1113*4882a593Smuzhiyun { .compatible = "rockchip,rk809" },
1114*4882a593Smuzhiyun { .compatible = "rockchip,rk816" },
1115*4882a593Smuzhiyun { .compatible = "rockchip,rk817" },
1116*4882a593Smuzhiyun { .compatible = "rockchip,rk818" },
1117*4882a593Smuzhiyun { },
1118*4882a593Smuzhiyun };
1119*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rk808_of_match);
1120*4882a593Smuzhiyun
rk808_probe(struct i2c_client * client,const struct i2c_device_id * id)1121*4882a593Smuzhiyun static int rk808_probe(struct i2c_client *client,
1122*4882a593Smuzhiyun const struct i2c_device_id *id)
1123*4882a593Smuzhiyun {
1124*4882a593Smuzhiyun struct device_node *np = client->dev.of_node;
1125*4882a593Smuzhiyun struct rk808 *rk808;
1126*4882a593Smuzhiyun const struct rk808_reg_data *pre_init_reg;
1127*4882a593Smuzhiyun const struct regmap_irq_chip *battery_irq_chip = NULL;
1128*4882a593Smuzhiyun const struct mfd_cell *cells;
1129*4882a593Smuzhiyun unsigned char pmic_id_msb, pmic_id_lsb;
1130*4882a593Smuzhiyun u8 on_source = 0, off_source = 0;
1131*4882a593Smuzhiyun unsigned int on, off;
1132*4882a593Smuzhiyun int pm_off = 0, msb, lsb;
1133*4882a593Smuzhiyun int nr_pre_init_regs;
1134*4882a593Smuzhiyun int nr_cells;
1135*4882a593Smuzhiyun int ret;
1136*4882a593Smuzhiyun int i;
1137*4882a593Smuzhiyun void (*of_property_prepare_fn)(struct rk808 *rk808,
1138*4882a593Smuzhiyun struct device *dev) = NULL;
1139*4882a593Smuzhiyun int (*pinctrl_init)(struct device *dev, struct rk808 *rk808) = NULL;
1140*4882a593Smuzhiyun void (*device_shutdown_fn)(void) = NULL;
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun rk808 = devm_kzalloc(&client->dev, sizeof(*rk808), GFP_KERNEL);
1143*4882a593Smuzhiyun if (!rk808)
1144*4882a593Smuzhiyun return -ENOMEM;
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun if (of_device_is_compatible(np, "rockchip,rk817") ||
1147*4882a593Smuzhiyun of_device_is_compatible(np, "rockchip,rk809")) {
1148*4882a593Smuzhiyun pmic_id_msb = RK817_ID_MSB;
1149*4882a593Smuzhiyun pmic_id_lsb = RK817_ID_LSB;
1150*4882a593Smuzhiyun } else {
1151*4882a593Smuzhiyun pmic_id_msb = RK808_ID_MSB;
1152*4882a593Smuzhiyun pmic_id_lsb = RK808_ID_LSB;
1153*4882a593Smuzhiyun }
1154*4882a593Smuzhiyun
1155*4882a593Smuzhiyun /* Read chip variant */
1156*4882a593Smuzhiyun msb = i2c_smbus_read_byte_data(client, pmic_id_msb);
1157*4882a593Smuzhiyun if (msb < 0) {
1158*4882a593Smuzhiyun dev_err(&client->dev, "failed to read the chip id at 0x%x\n",
1159*4882a593Smuzhiyun RK808_ID_MSB);
1160*4882a593Smuzhiyun return msb;
1161*4882a593Smuzhiyun }
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb);
1164*4882a593Smuzhiyun if (lsb < 0) {
1165*4882a593Smuzhiyun dev_err(&client->dev, "failed to read the chip id at 0x%x\n",
1166*4882a593Smuzhiyun RK808_ID_LSB);
1167*4882a593Smuzhiyun return lsb;
1168*4882a593Smuzhiyun }
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun rk808->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
1171*4882a593Smuzhiyun dev_info(&client->dev, "chip id: 0x%x\n", (unsigned int)rk808->variant);
1172*4882a593Smuzhiyun
1173*4882a593Smuzhiyun switch (rk808->variant) {
1174*4882a593Smuzhiyun case RK805_ID:
1175*4882a593Smuzhiyun rk808->regmap_cfg = &rk805_regmap_config;
1176*4882a593Smuzhiyun rk808->regmap_irq_chip = &rk805_irq_chip;
1177*4882a593Smuzhiyun pre_init_reg = rk805_pre_init_reg;
1178*4882a593Smuzhiyun nr_pre_init_regs = ARRAY_SIZE(rk805_pre_init_reg);
1179*4882a593Smuzhiyun cells = rk805s;
1180*4882a593Smuzhiyun nr_cells = ARRAY_SIZE(rk805s);
1181*4882a593Smuzhiyun on_source = RK805_ON_SOURCE_REG;
1182*4882a593Smuzhiyun off_source = RK805_OFF_SOURCE_REG;
1183*4882a593Smuzhiyun suspend_reg = rk805_suspend_reg;
1184*4882a593Smuzhiyun suspend_reg_num = ARRAY_SIZE(rk805_suspend_reg);
1185*4882a593Smuzhiyun resume_reg = rk805_resume_reg;
1186*4882a593Smuzhiyun resume_reg_num = ARRAY_SIZE(rk805_resume_reg);
1187*4882a593Smuzhiyun device_shutdown_fn = rk8xx_device_shutdown;
1188*4882a593Smuzhiyun rk808->pm_pwroff_prep_fn = rk805_device_shutdown_prepare;
1189*4882a593Smuzhiyun break;
1190*4882a593Smuzhiyun case RK808_ID:
1191*4882a593Smuzhiyun rk808->regmap_cfg = &rk808_regmap_config;
1192*4882a593Smuzhiyun rk808->regmap_irq_chip = &rk808_irq_chip;
1193*4882a593Smuzhiyun pre_init_reg = rk808_pre_init_reg;
1194*4882a593Smuzhiyun nr_pre_init_regs = ARRAY_SIZE(rk808_pre_init_reg);
1195*4882a593Smuzhiyun cells = rk808s;
1196*4882a593Smuzhiyun nr_cells = ARRAY_SIZE(rk808s);
1197*4882a593Smuzhiyun device_shutdown_fn = rk8xx_device_shutdown;
1198*4882a593Smuzhiyun break;
1199*4882a593Smuzhiyun case RK816_ID:
1200*4882a593Smuzhiyun rk808->regmap_cfg = &rk816_regmap_config;
1201*4882a593Smuzhiyun rk808->regmap_irq_chip = &rk816_irq_chip;
1202*4882a593Smuzhiyun battery_irq_chip = &rk816_battery_irq_chip;
1203*4882a593Smuzhiyun pre_init_reg = rk816_pre_init_reg;
1204*4882a593Smuzhiyun nr_pre_init_regs = ARRAY_SIZE(rk816_pre_init_reg);
1205*4882a593Smuzhiyun cells = rk816s;
1206*4882a593Smuzhiyun nr_cells = ARRAY_SIZE(rk816s);
1207*4882a593Smuzhiyun on_source = RK816_ON_SOURCE_REG;
1208*4882a593Smuzhiyun off_source = RK816_OFF_SOURCE_REG;
1209*4882a593Smuzhiyun suspend_reg = rk816_suspend_reg;
1210*4882a593Smuzhiyun suspend_reg_num = ARRAY_SIZE(rk816_suspend_reg);
1211*4882a593Smuzhiyun resume_reg = rk816_resume_reg;
1212*4882a593Smuzhiyun resume_reg_num = ARRAY_SIZE(rk816_resume_reg);
1213*4882a593Smuzhiyun device_shutdown_fn = rk8xx_device_shutdown;
1214*4882a593Smuzhiyun break;
1215*4882a593Smuzhiyun case RK818_ID:
1216*4882a593Smuzhiyun rk808->regmap_cfg = &rk818_regmap_config;
1217*4882a593Smuzhiyun rk808->regmap_irq_chip = &rk818_irq_chip;
1218*4882a593Smuzhiyun pre_init_reg = rk818_pre_init_reg;
1219*4882a593Smuzhiyun nr_pre_init_regs = ARRAY_SIZE(rk818_pre_init_reg);
1220*4882a593Smuzhiyun cells = rk818s;
1221*4882a593Smuzhiyun nr_cells = ARRAY_SIZE(rk818s);
1222*4882a593Smuzhiyun on_source = RK818_ON_SOURCE_REG;
1223*4882a593Smuzhiyun off_source = RK818_OFF_SOURCE_REG;
1224*4882a593Smuzhiyun suspend_reg = rk818_suspend_reg;
1225*4882a593Smuzhiyun suspend_reg_num = ARRAY_SIZE(rk818_suspend_reg);
1226*4882a593Smuzhiyun resume_reg = rk818_resume_reg;
1227*4882a593Smuzhiyun resume_reg_num = ARRAY_SIZE(rk818_resume_reg);
1228*4882a593Smuzhiyun device_shutdown_fn = rk8xx_device_shutdown;
1229*4882a593Smuzhiyun break;
1230*4882a593Smuzhiyun case RK809_ID:
1231*4882a593Smuzhiyun case RK817_ID:
1232*4882a593Smuzhiyun rk808->regmap_cfg = &rk817_regmap_config;
1233*4882a593Smuzhiyun rk808->regmap_irq_chip = &rk817_irq_chip;
1234*4882a593Smuzhiyun pre_init_reg = rk817_pre_init_reg;
1235*4882a593Smuzhiyun nr_pre_init_regs = ARRAY_SIZE(rk817_pre_init_reg);
1236*4882a593Smuzhiyun cells = rk817s;
1237*4882a593Smuzhiyun nr_cells = ARRAY_SIZE(rk817s);
1238*4882a593Smuzhiyun on_source = RK817_ON_SOURCE_REG;
1239*4882a593Smuzhiyun off_source = RK817_OFF_SOURCE_REG;
1240*4882a593Smuzhiyun rk808->pm_pwroff_prep_fn = rk817_shutdown_prepare;
1241*4882a593Smuzhiyun of_property_prepare_fn = rk817_of_property_prepare;
1242*4882a593Smuzhiyun pinctrl_init = rk817_pinctrl_init;
1243*4882a593Smuzhiyun break;
1244*4882a593Smuzhiyun default:
1245*4882a593Smuzhiyun dev_err(&client->dev, "Unsupported RK8XX ID %lu\n",
1246*4882a593Smuzhiyun rk808->variant);
1247*4882a593Smuzhiyun return -EINVAL;
1248*4882a593Smuzhiyun }
1249*4882a593Smuzhiyun
1250*4882a593Smuzhiyun rk808->i2c = client;
1251*4882a593Smuzhiyun rk808_i2c_client = client;
1252*4882a593Smuzhiyun i2c_set_clientdata(client, rk808);
1253*4882a593Smuzhiyun
1254*4882a593Smuzhiyun rk808->regmap = devm_regmap_init_i2c(client, rk808->regmap_cfg);
1255*4882a593Smuzhiyun if (IS_ERR(rk808->regmap)) {
1256*4882a593Smuzhiyun dev_err(&client->dev, "regmap initialization failed\n");
1257*4882a593Smuzhiyun return PTR_ERR(rk808->regmap);
1258*4882a593Smuzhiyun }
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun if (on_source && off_source) {
1261*4882a593Smuzhiyun ret = regmap_read(rk808->regmap, on_source, &on);
1262*4882a593Smuzhiyun if (ret) {
1263*4882a593Smuzhiyun dev_err(&client->dev, "read 0x%x failed\n", on_source);
1264*4882a593Smuzhiyun return ret;
1265*4882a593Smuzhiyun }
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun ret = regmap_read(rk808->regmap, off_source, &off);
1268*4882a593Smuzhiyun if (ret) {
1269*4882a593Smuzhiyun dev_err(&client->dev, "read 0x%x failed\n", off_source);
1270*4882a593Smuzhiyun return ret;
1271*4882a593Smuzhiyun }
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun dev_info(&client->dev, "source: on=0x%02x, off=0x%02x\n",
1274*4882a593Smuzhiyun on, off);
1275*4882a593Smuzhiyun }
1276*4882a593Smuzhiyun
1277*4882a593Smuzhiyun if (!client->irq) {
1278*4882a593Smuzhiyun dev_err(&client->dev, "No interrupt support, no core IRQ\n");
1279*4882a593Smuzhiyun return -EINVAL;
1280*4882a593Smuzhiyun }
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun if (of_property_prepare_fn)
1283*4882a593Smuzhiyun of_property_prepare_fn(rk808, &client->dev);
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun for (i = 0; i < nr_pre_init_regs; i++) {
1286*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap,
1287*4882a593Smuzhiyun pre_init_reg[i].addr,
1288*4882a593Smuzhiyun pre_init_reg[i].mask,
1289*4882a593Smuzhiyun pre_init_reg[i].value);
1290*4882a593Smuzhiyun if (ret) {
1291*4882a593Smuzhiyun dev_err(&client->dev,
1292*4882a593Smuzhiyun "0x%x write err\n",
1293*4882a593Smuzhiyun pre_init_reg[i].addr);
1294*4882a593Smuzhiyun return ret;
1295*4882a593Smuzhiyun }
1296*4882a593Smuzhiyun }
1297*4882a593Smuzhiyun
1298*4882a593Smuzhiyun if (pinctrl_init) {
1299*4882a593Smuzhiyun ret = pinctrl_init(&client->dev, rk808);
1300*4882a593Smuzhiyun if (ret)
1301*4882a593Smuzhiyun return ret;
1302*4882a593Smuzhiyun }
1303*4882a593Smuzhiyun
1304*4882a593Smuzhiyun ret = regmap_add_irq_chip(rk808->regmap, client->irq,
1305*4882a593Smuzhiyun IRQF_ONESHOT | IRQF_SHARED, -1,
1306*4882a593Smuzhiyun rk808->regmap_irq_chip, &rk808->irq_data);
1307*4882a593Smuzhiyun if (ret) {
1308*4882a593Smuzhiyun dev_err(&client->dev, "Failed to add irq_chip %d\n", ret);
1309*4882a593Smuzhiyun return ret;
1310*4882a593Smuzhiyun }
1311*4882a593Smuzhiyun
1312*4882a593Smuzhiyun if (battery_irq_chip) {
1313*4882a593Smuzhiyun ret = regmap_add_irq_chip(rk808->regmap, client->irq,
1314*4882a593Smuzhiyun IRQF_ONESHOT | IRQF_SHARED, -1,
1315*4882a593Smuzhiyun battery_irq_chip,
1316*4882a593Smuzhiyun &rk808->battery_irq_data);
1317*4882a593Smuzhiyun if (ret) {
1318*4882a593Smuzhiyun dev_err(&client->dev,
1319*4882a593Smuzhiyun "Failed to add batterry irq_chip %d\n", ret);
1320*4882a593Smuzhiyun regmap_del_irq_chip(client->irq, rk808->irq_data);
1321*4882a593Smuzhiyun return ret;
1322*4882a593Smuzhiyun }
1323*4882a593Smuzhiyun }
1324*4882a593Smuzhiyun
1325*4882a593Smuzhiyun ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE,
1326*4882a593Smuzhiyun cells, nr_cells, NULL, 0,
1327*4882a593Smuzhiyun regmap_irq_get_domain(rk808->irq_data));
1328*4882a593Smuzhiyun if (ret) {
1329*4882a593Smuzhiyun dev_err(&client->dev, "failed to add MFD devices %d\n", ret);
1330*4882a593Smuzhiyun goto err_irq;
1331*4882a593Smuzhiyun }
1332*4882a593Smuzhiyun
1333*4882a593Smuzhiyun pm_off = of_property_read_bool(np, "rockchip,system-power-controller");
1334*4882a593Smuzhiyun if (pm_off) {
1335*4882a593Smuzhiyun if (!pm_power_off_prepare)
1336*4882a593Smuzhiyun pm_power_off_prepare = rk808->pm_pwroff_prep_fn;
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun if (device_shutdown_fn) {
1339*4882a593Smuzhiyun register_syscore_ops(&rk808_syscore_ops);
1340*4882a593Smuzhiyun /* power off system in the syscore shutdown ! */
1341*4882a593Smuzhiyun pm_shutdown = device_shutdown_fn;
1342*4882a593Smuzhiyun }
1343*4882a593Smuzhiyun }
1344*4882a593Smuzhiyun
1345*4882a593Smuzhiyun rk8xx_kobj = kobject_create_and_add("rk8xx", NULL);
1346*4882a593Smuzhiyun if (rk8xx_kobj) {
1347*4882a593Smuzhiyun ret = sysfs_create_file(rk8xx_kobj, &rk8xx_attrs.attr);
1348*4882a593Smuzhiyun if (ret)
1349*4882a593Smuzhiyun dev_err(&client->dev, "create rk8xx sysfs error\n");
1350*4882a593Smuzhiyun }
1351*4882a593Smuzhiyun
1352*4882a593Smuzhiyun if (!pm_power_off)
1353*4882a593Smuzhiyun pm_power_off = rk808_pm_power_off_dummy;
1354*4882a593Smuzhiyun
1355*4882a593Smuzhiyun return 0;
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun err_irq:
1358*4882a593Smuzhiyun regmap_del_irq_chip(client->irq, rk808->irq_data);
1359*4882a593Smuzhiyun if (battery_irq_chip)
1360*4882a593Smuzhiyun regmap_del_irq_chip(client->irq, rk808->battery_irq_data);
1361*4882a593Smuzhiyun return ret;
1362*4882a593Smuzhiyun }
1363*4882a593Smuzhiyun
rk808_remove(struct i2c_client * client)1364*4882a593Smuzhiyun static int rk808_remove(struct i2c_client *client)
1365*4882a593Smuzhiyun {
1366*4882a593Smuzhiyun struct rk808 *rk808 = i2c_get_clientdata(client);
1367*4882a593Smuzhiyun
1368*4882a593Smuzhiyun regmap_del_irq_chip(client->irq, rk808->irq_data);
1369*4882a593Smuzhiyun
1370*4882a593Smuzhiyun /**
1371*4882a593Smuzhiyun * pm_power_off may points to a function from another module.
1372*4882a593Smuzhiyun * Check if the pointer is set by us and only then overwrite it.
1373*4882a593Smuzhiyun */
1374*4882a593Smuzhiyun if (pm_power_off == rk808_pm_power_off_dummy)
1375*4882a593Smuzhiyun pm_power_off = NULL;
1376*4882a593Smuzhiyun
1377*4882a593Smuzhiyun /**
1378*4882a593Smuzhiyun * As above, check if the pointer is set by us before overwrite.
1379*4882a593Smuzhiyun */
1380*4882a593Smuzhiyun if (rk808->pm_pwroff_prep_fn &&
1381*4882a593Smuzhiyun pm_power_off_prepare == rk808->pm_pwroff_prep_fn)
1382*4882a593Smuzhiyun pm_power_off_prepare = NULL;
1383*4882a593Smuzhiyun
1384*4882a593Smuzhiyun if (pm_shutdown)
1385*4882a593Smuzhiyun unregister_syscore_ops(&rk808_syscore_ops);
1386*4882a593Smuzhiyun
1387*4882a593Smuzhiyun return 0;
1388*4882a593Smuzhiyun }
1389*4882a593Smuzhiyun
rk8xx_suspend(struct device * dev)1390*4882a593Smuzhiyun static int __maybe_unused rk8xx_suspend(struct device *dev)
1391*4882a593Smuzhiyun {
1392*4882a593Smuzhiyun struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
1393*4882a593Smuzhiyun int i, ret = 0;
1394*4882a593Smuzhiyun int value;
1395*4882a593Smuzhiyun
1396*4882a593Smuzhiyun for (i = 0; i < suspend_reg_num; i++) {
1397*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap,
1398*4882a593Smuzhiyun suspend_reg[i].addr,
1399*4882a593Smuzhiyun suspend_reg[i].mask,
1400*4882a593Smuzhiyun suspend_reg[i].value);
1401*4882a593Smuzhiyun if (ret) {
1402*4882a593Smuzhiyun dev_err(dev, "0x%x write err\n",
1403*4882a593Smuzhiyun suspend_reg[i].addr);
1404*4882a593Smuzhiyun return ret;
1405*4882a593Smuzhiyun }
1406*4882a593Smuzhiyun }
1407*4882a593Smuzhiyun
1408*4882a593Smuzhiyun switch (rk808->variant) {
1409*4882a593Smuzhiyun case RK805_ID:
1410*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap,
1411*4882a593Smuzhiyun RK805_GPIO_IO_POL_REG,
1412*4882a593Smuzhiyun SLP_SD_MSK,
1413*4882a593Smuzhiyun SLEEP_FUN);
1414*4882a593Smuzhiyun break;
1415*4882a593Smuzhiyun case RK809_ID:
1416*4882a593Smuzhiyun case RK817_ID:
1417*4882a593Smuzhiyun if (rk808->pins && rk808->pins->p && rk808->pins->sleep) {
1418*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap,
1419*4882a593Smuzhiyun RK817_SYS_CFG(3),
1420*4882a593Smuzhiyun RK817_SLPPIN_FUNC_MSK,
1421*4882a593Smuzhiyun SLPPIN_NULL_FUN);
1422*4882a593Smuzhiyun if (ret) {
1423*4882a593Smuzhiyun dev_err(dev, "suspend: config SLPPIN_NULL_FUN error!\n");
1424*4882a593Smuzhiyun return ret;
1425*4882a593Smuzhiyun }
1426*4882a593Smuzhiyun
1427*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap,
1428*4882a593Smuzhiyun RK817_SYS_CFG(3),
1429*4882a593Smuzhiyun RK817_SLPPOL_MSK,
1430*4882a593Smuzhiyun RK817_SLPPOL_H);
1431*4882a593Smuzhiyun if (ret) {
1432*4882a593Smuzhiyun dev_err(dev, "suspend: config RK817_SLPPOL_H error!\n");
1433*4882a593Smuzhiyun return ret;
1434*4882a593Smuzhiyun }
1435*4882a593Smuzhiyun
1436*4882a593Smuzhiyun /* pmic need the SCL clock to synchronize register */
1437*4882a593Smuzhiyun regmap_read(rk808->regmap, RK817_SYS_STS, &value);
1438*4882a593Smuzhiyun mdelay(2);
1439*4882a593Smuzhiyun ret = pinctrl_select_state(rk808->pins->p, rk808->pins->sleep);
1440*4882a593Smuzhiyun if (ret) {
1441*4882a593Smuzhiyun dev_err(dev, "failed to act slp pinctrl state\n");
1442*4882a593Smuzhiyun return ret;
1443*4882a593Smuzhiyun }
1444*4882a593Smuzhiyun }
1445*4882a593Smuzhiyun break;
1446*4882a593Smuzhiyun default:
1447*4882a593Smuzhiyun break;
1448*4882a593Smuzhiyun }
1449*4882a593Smuzhiyun
1450*4882a593Smuzhiyun return ret;
1451*4882a593Smuzhiyun }
1452*4882a593Smuzhiyun
rk8xx_resume(struct device * dev)1453*4882a593Smuzhiyun static int __maybe_unused rk8xx_resume(struct device *dev)
1454*4882a593Smuzhiyun {
1455*4882a593Smuzhiyun struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
1456*4882a593Smuzhiyun int i, ret = 0;
1457*4882a593Smuzhiyun int value;
1458*4882a593Smuzhiyun
1459*4882a593Smuzhiyun for (i = 0; i < resume_reg_num; i++) {
1460*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap,
1461*4882a593Smuzhiyun resume_reg[i].addr,
1462*4882a593Smuzhiyun resume_reg[i].mask,
1463*4882a593Smuzhiyun resume_reg[i].value);
1464*4882a593Smuzhiyun if (ret) {
1465*4882a593Smuzhiyun dev_err(dev, "0x%x write err\n",
1466*4882a593Smuzhiyun resume_reg[i].addr);
1467*4882a593Smuzhiyun return ret;
1468*4882a593Smuzhiyun }
1469*4882a593Smuzhiyun }
1470*4882a593Smuzhiyun
1471*4882a593Smuzhiyun switch (rk808->variant) {
1472*4882a593Smuzhiyun case RK809_ID:
1473*4882a593Smuzhiyun case RK817_ID:
1474*4882a593Smuzhiyun if (rk808->pins && rk808->pins->p && rk808->pins->reset) {
1475*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap,
1476*4882a593Smuzhiyun RK817_SYS_CFG(3),
1477*4882a593Smuzhiyun RK817_SLPPIN_FUNC_MSK,
1478*4882a593Smuzhiyun SLPPIN_NULL_FUN);
1479*4882a593Smuzhiyun if (ret) {
1480*4882a593Smuzhiyun dev_err(dev, "resume: config SLPPIN_NULL_FUN error!\n");
1481*4882a593Smuzhiyun return ret;
1482*4882a593Smuzhiyun }
1483*4882a593Smuzhiyun
1484*4882a593Smuzhiyun ret = regmap_update_bits(rk808->regmap,
1485*4882a593Smuzhiyun RK817_SYS_CFG(3),
1486*4882a593Smuzhiyun RK817_SLPPOL_MSK,
1487*4882a593Smuzhiyun RK817_SLPPOL_L);
1488*4882a593Smuzhiyun if (ret) {
1489*4882a593Smuzhiyun dev_err(dev, "resume: config RK817_SLPPOL_L error!\n");
1490*4882a593Smuzhiyun return ret;
1491*4882a593Smuzhiyun }
1492*4882a593Smuzhiyun
1493*4882a593Smuzhiyun /* pmic need the SCL clock to synchronize register */
1494*4882a593Smuzhiyun regmap_read(rk808->regmap, RK817_SYS_STS, &value);
1495*4882a593Smuzhiyun mdelay(2);
1496*4882a593Smuzhiyun ret = pinctrl_select_state(rk808->pins->p, rk808->pins->reset);
1497*4882a593Smuzhiyun if (ret)
1498*4882a593Smuzhiyun dev_dbg(dev, "failed to act reset pinctrl state\n");
1499*4882a593Smuzhiyun }
1500*4882a593Smuzhiyun break;
1501*4882a593Smuzhiyun default:
1502*4882a593Smuzhiyun break;
1503*4882a593Smuzhiyun }
1504*4882a593Smuzhiyun
1505*4882a593Smuzhiyun return ret;
1506*4882a593Smuzhiyun }
1507*4882a593Smuzhiyun SIMPLE_DEV_PM_OPS(rk8xx_pm_ops, rk8xx_suspend, rk8xx_resume);
1508*4882a593Smuzhiyun
1509*4882a593Smuzhiyun static struct i2c_driver rk808_i2c_driver = {
1510*4882a593Smuzhiyun .driver = {
1511*4882a593Smuzhiyun .name = "rk808",
1512*4882a593Smuzhiyun .of_match_table = rk808_of_match,
1513*4882a593Smuzhiyun .pm = &rk8xx_pm_ops,
1514*4882a593Smuzhiyun },
1515*4882a593Smuzhiyun .probe = rk808_probe,
1516*4882a593Smuzhiyun .remove = rk808_remove,
1517*4882a593Smuzhiyun };
1518*4882a593Smuzhiyun
1519*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
rk808_i2c_driver_init(void)1520*4882a593Smuzhiyun static int __init rk808_i2c_driver_init(void)
1521*4882a593Smuzhiyun {
1522*4882a593Smuzhiyun return i2c_add_driver(&rk808_i2c_driver);
1523*4882a593Smuzhiyun }
1524*4882a593Smuzhiyun subsys_initcall(rk808_i2c_driver_init);
1525*4882a593Smuzhiyun
rk808_i2c_driver_exit(void)1526*4882a593Smuzhiyun static void __exit rk808_i2c_driver_exit(void)
1527*4882a593Smuzhiyun {
1528*4882a593Smuzhiyun i2c_del_driver(&rk808_i2c_driver);
1529*4882a593Smuzhiyun }
1530*4882a593Smuzhiyun module_exit(rk808_i2c_driver_exit);
1531*4882a593Smuzhiyun #else
1532*4882a593Smuzhiyun module_i2c_driver(rk808_i2c_driver);
1533*4882a593Smuzhiyun #endif
1534*4882a593Smuzhiyun
1535*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1536*4882a593Smuzhiyun MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1537*4882a593Smuzhiyun MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>");
1538*4882a593Smuzhiyun MODULE_AUTHOR("Wadim Egorov <w.egorov@phytec.de>");
1539*4882a593Smuzhiyun MODULE_DESCRIPTION("RK808/RK818 PMIC driver");
1540