1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2016 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_ARCH_WDT_H 8*4882a593Smuzhiyun #define _ASM_ARCH_WDT_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define WDT_BASE 0x1e785000 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Special value that needs to be written to counter_restart register to 14*4882a593Smuzhiyun * (re)start the timer 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define WDT_COUNTER_RESTART_VAL 0x4755 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Control register */ 19*4882a593Smuzhiyun #define WDT_CTRL_RESET_MODE_SHIFT 5 20*4882a593Smuzhiyun #define WDT_CTRL_RESET_MODE_MASK 3 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define WDT_CTRL_EN (1 << 0) 23*4882a593Smuzhiyun #define WDT_CTRL_RESET (1 << 1) 24*4882a593Smuzhiyun #define WDT_CTRL_CLK1MHZ (1 << 4) 25*4882a593Smuzhiyun #define WDT_CTRL_2ND_BOOT (1 << 7) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Values for Reset Mode */ 28*4882a593Smuzhiyun #define WDT_CTRL_RESET_SOC 0 29*4882a593Smuzhiyun #define WDT_CTRL_RESET_CHIP 1 30*4882a593Smuzhiyun #define WDT_CTRL_RESET_CPU 2 31*4882a593Smuzhiyun #define WDT_CTRL_RESET_MASK 3 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Reset Mask register */ 34*4882a593Smuzhiyun #define WDT_RESET_ARM (1 << 0) 35*4882a593Smuzhiyun #define WDT_RESET_COPROC (1 << 1) 36*4882a593Smuzhiyun #define WDT_RESET_SDRAM (1 << 2) 37*4882a593Smuzhiyun #define WDT_RESET_AHB (1 << 3) 38*4882a593Smuzhiyun #define WDT_RESET_I2C (1 << 4) 39*4882a593Smuzhiyun #define WDT_RESET_MAC1 (1 << 5) 40*4882a593Smuzhiyun #define WDT_RESET_MAC2 (1 << 6) 41*4882a593Smuzhiyun #define WDT_RESET_GCRT (1 << 7) 42*4882a593Smuzhiyun #define WDT_RESET_USB20 (1 << 8) 43*4882a593Smuzhiyun #define WDT_RESET_USB11_HOST (1 << 9) 44*4882a593Smuzhiyun #define WDT_RESET_USB11_EHCI2 (1 << 10) 45*4882a593Smuzhiyun #define WDT_RESET_VIDEO (1 << 11) 46*4882a593Smuzhiyun #define WDT_RESET_HAC (1 << 12) 47*4882a593Smuzhiyun #define WDT_RESET_LPC (1 << 13) 48*4882a593Smuzhiyun #define WDT_RESET_SDSDIO (1 << 14) 49*4882a593Smuzhiyun #define WDT_RESET_MIC (1 << 15) 50*4882a593Smuzhiyun #define WDT_RESET_CRT2C (1 << 16) 51*4882a593Smuzhiyun #define WDT_RESET_PWM (1 << 17) 52*4882a593Smuzhiyun #define WDT_RESET_PECI (1 << 18) 53*4882a593Smuzhiyun #define WDT_RESET_JTAG (1 << 19) 54*4882a593Smuzhiyun #define WDT_RESET_ADC (1 << 20) 55*4882a593Smuzhiyun #define WDT_RESET_GPIO (1 << 21) 56*4882a593Smuzhiyun #define WDT_RESET_MCTP (1 << 22) 57*4882a593Smuzhiyun #define WDT_RESET_XDMA (1 << 23) 58*4882a593Smuzhiyun #define WDT_RESET_SPI (1 << 24) 59*4882a593Smuzhiyun #define WDT_RESET_MISC (1 << 25) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 62*4882a593Smuzhiyun struct ast_wdt { 63*4882a593Smuzhiyun u32 counter_status; 64*4882a593Smuzhiyun u32 counter_reload_val; 65*4882a593Smuzhiyun u32 counter_restart; 66*4882a593Smuzhiyun u32 ctrl; 67*4882a593Smuzhiyun u32 timeout_status; 68*4882a593Smuzhiyun u32 clr_timeout_status; 69*4882a593Smuzhiyun u32 reset_width; 70*4882a593Smuzhiyun /* On pre-ast2500 SoCs this register is reserved. */ 71*4882a593Smuzhiyun u32 reset_mask; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /** 75*4882a593Smuzhiyun * Given flags parameter passed to wdt_reset or wdt_start uclass functions, 76*4882a593Smuzhiyun * gets Reset Mode value from it. 77*4882a593Smuzhiyun * 78*4882a593Smuzhiyun * @flags: flags parameter passed into wdt_reset or wdt_start 79*4882a593Smuzhiyun * @return Reset Mode value 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun u32 ast_reset_mode_from_flags(ulong flags); 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /** 84*4882a593Smuzhiyun * Given flags parameter passed to wdt_reset or wdt_start uclass functions, 85*4882a593Smuzhiyun * gets Reset Mask value from it. Reset Mask is only supported on ast2500 86*4882a593Smuzhiyun * 87*4882a593Smuzhiyun * @flags: flags parameter passed into wdt_reset or wdt_start 88*4882a593Smuzhiyun * @return Reset Mask value 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun u32 ast_reset_mask_from_flags(ulong flags); 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /** 93*4882a593Smuzhiyun * Given Reset Mask and Reset Mode values, converts them to flags, 94*4882a593Smuzhiyun * suitable for passing into wdt_start or wdt_reset uclass functions. 95*4882a593Smuzhiyun * 96*4882a593Smuzhiyun * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they 97*4882a593Smuzhiyun * can both be packed into single 32 bits wide value. 98*4882a593Smuzhiyun * 99*4882a593Smuzhiyun * @reset_mode: Reset Mode 100*4882a593Smuzhiyun * @reset_mask: Reset Mask 101*4882a593Smuzhiyun */ 102*4882a593Smuzhiyun ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask); 103*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #endif /* _ASM_ARCH_WDT_H */ 106