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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Daxis,artpec6-pcie.txt1 * Axis ARTPEC-6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
13 - reg-names: Must include the following entries:
14 - "dbi"
[all …]
H A Ddesignware-pcie.txt1 * Synopsys DesignWare PCIe interface
4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
17 - device_type: set to "pci"
18 - ranges: ranges for the PCI memory and I/O regions
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H A Dintel-gw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCIe RC controller on Intel Gateway SoCs
10 - Dilip Kota <eswara.kota@linux.intel.com>
16 const: intel,lgm-pcie
18 - compatible
23 - const: intel,lgm-pcie
24 - const: snps,dw-pcie
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H A Dspear13xx-pcie.txt1 SPEAr13XX PCIe DT detail:
4 SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
8 - compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
9 - phys : phandle to PHY node associated with PCIe controller
10 - phy-names : must be "pcie-phy"
11 - All other definitions as per generic PCI bindings
14 - st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
H A Dqcom,pcie.txt3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sdm845" for sdm845
[all …]
H A Dhisilicon-pcie.txt1 HiSilicon Hip05 and Hip06 PCIe host bridge DT description
3 HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
4 It shares common functions with the PCIe DesignWare core driver and inherits
6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
12 - reg: Should contain rc_dbi, config registers location and length.
13 - reg-names: Must include the following entries:
15 "config": PCIe configuration space registers.
16 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
17 - port-id: Should be 0, 1, 2 or 3.
[all …]
H A Dsamsung,exynos5440-pcie.txt1 * Samsung Exynos 5440 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "samsung,exynos5440-pcie"
8 - reg: base addresses and lengths of the PCIe controller,
9 - reg-names : First name should be set to "elbi".
12 NOTE: When using the "config" property, reg-names must be set.
13 - interrupts: A list of interrupt outputs for level interrupt,
15 - phys: From PHY binding. Phandle for the generic PHY.
16 Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
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H A Damlogic,meson-pcie.txt1 Amlogic Meson AXG DWC PCIE SoC controller
3 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
4 It shares common functions with the PCIe DesignWare core driver and
6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible:
13 - "amlogic,axg-pcie" for AXG SoC Family
14 - "amlogic,g12a-pcie" for G12A SoC Family
16 - reg:
18 - reg-names: Must be
19 - "elbi" External local bus interface registers
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H A Dpci-armada8k.txt1 * Marvell Armada 7K/8K PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "marvell,armada8k-pcie"
8 - reg: must contain two register regions
9 - the control register region
10 - the config space region
11 - reg-names:
12 - "ctrl" for the control register region
13 - "config" for the config space region
[all …]
/OK3568_Linux_fs/kernel/drivers/pci/controller/dwc/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
4 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
5 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
6 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
7 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
8 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
9 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
10 obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
23 bool "TI DRA7xx PCIe controller Host Mode"
31 Enables support for the PCIe controller in the DRA7xx SoC to work in
32 host mode. There are two instances of PCIe controller in DRA7xx.
34 host-specific features PCI_DRA7XX_HOST must be selected and in order
35 to enable device-specific features PCI_DRA7XX_EP must be selected.
39 bool "TI DRA7xx PCIe controller Endpoint Mode"
46 Enables support for the PCIe controller in the DRA7xx SoC to work in
47 endpoint mode. There are two instances of PCIe controller in DRA7xx.
49 host-specific features PCI_DRA7XX_HOST must be selected and in order
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H A Dpcie-designware-plat.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe RC driver for Synopsys DesignWare Core
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
22 #include "pcie-designware.h"
49 pp->num_vectors = MAX_MSI_IRQS; in dw_plat_set_num_vectors()
89 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in dw_plat_pcie_ep_raise_irq()
116 struct dw_pcie *pci = dw_plat_pcie->pci; in dw_plat_add_pcie_port()
117 struct pcie_port *pp = &pci->pp; in dw_plat_add_pcie_port()
118 struct device *dev = &pdev->dev; in dw_plat_add_pcie_port()
121 pp->irq = platform_get_irq(pdev, 1); in dw_plat_add_pcie_port()
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H A Dpcie-al.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
12 #include <linux/pci-ecam.h>
13 #include <linux/pci-acpi.h>
25 struct pci_config_window *cfg = bus->sysdata; in al_pcie_map_bus()
26 struct al_pcie_acpi *pcie = cfg->priv; in al_pcie_map_bus() local
27 void __iomem *dbi_base = pcie->dbi_base; in al_pcie_map_bus()
29 if (bus->number == cfg->busr.start) { in al_pcie_map_bus()
31 * The DW PCIe core doesn't filter out transactions to other in al_pcie_map_bus()
45 struct device *dev = cfg->parent; in al_pcie_init()
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/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/pci/
H A Darmada8k-pcie.txt1 Armada-8K PCIe DT details:
4 Armada-8k uses synopsis designware PCIe controller.
7 - compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie".
8 - reg: base addresses and lengths of the pcie control and global control registers.
10 points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below.
11 - interrupt-map-mask and interrupt-map, standard PCI properties to
12 define the mapping of the PCIe interface to interrupt numbers.
13 - All other definitions as per generic PCI bindings
15 "Documentation/devicetree/bindings/pci/designware-pcie.txt"
18 PHY support is still not supported for armada-8k, once it will, the following parameters can be use…
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/OK3568_Linux_fs/kernel/drivers/dma/dw-edma/
H A Ddw-edma-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA PCIe driver
14 #include <linux/pci-epf.h>
17 #include "dw-edma-core.h"
69 const struct dw_edma_pcie_data *pdata = (void *)pid->driver_data; in dw_edma_pcie_probe()
70 struct device *dev = &pdev->dev; in dw_edma_pcie_probe()
73 struct dw_edma *dw; in dw_edma_pcie_probe() local
83 err = pcim_iomap_regions(pdev, BIT(pdata->rg_bar) | in dw_edma_pcie_probe()
84 BIT(pdata->ll_bar) | in dw_edma_pcie_probe()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_DW_EDMA) += dw-edma.o
4 dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o
5 dw-edma-objs := dw-edma-core.o \
6 dw-edma-v0-core.o $(dw-edma-y)
7 obj-$(CONFIG_DW_EDMA_PCIE) += dw-edma-pcie.o
/OK3568_Linux_fs/kernel/drivers/pci/controller/
H A Dpcie-altera.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
60 #define TLP_CFG_DW0(pcie, cfg) \ argument
63 #define TLP_CFG_DW1(pcie, tag, be) \ argument
64 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dfsl-ls2080a.dtsi4 * Copyright 2013-2015 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
18 /* DRAM space - 1, size : 2 GB DRAM */
21 gic: interrupt-controller@6000000 {
22 compatible = "arm,gic-v3";
25 #interrupt-cells = <3>;
26 interrupt-controller;
[all …]
H A Dfsl-ls1043a.dtsi2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * Copyright (C) 2014-2015, Freescale Semiconductor
17 interrupt-parent = <&gic>;
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <100000000>;
23 clock-output-names = "sysclk";
26 gic: interrupt-controller@1400000 {
27 compatible = "arm,gic-400";
28 #interrupt-cells = <3>;
[all …]
H A Dfsl-ls1046a.dtsi2 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
17 interrupt-parent = <&gic>;
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <100000000>;
23 clock-output-names = "sysclk";
26 gic: interrupt-controller@1400000 {
27 compatible = "arm,gic-400";
28 #interrupt-cells = <3>;
29 interrupt-controller;
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H A Darmada-cp110-slave.dtsi4 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/comphy/comphy_data.h>
50 cp110-slave {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
57 config-space {
58 #address-cells = <1>;
59 #size-cells = <1>;
[all …]
H A Darmada-cp110-master.dtsi4 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/comphy/comphy_data.h>
50 cp110-master {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
57 config-space {
58 #address-cells = <1>;
59 #size-cells = <1>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/marvell/
H A Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
[all …]
H A Darmada-39x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
37 compatible = "arm,cortex-a9";
[all …]

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