1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2016 Marvell Technology Group Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 5*4882a593Smuzhiyun * of the GPLv2 or the X11 license, at your option. Note that this dual 6*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 7*4882a593Smuzhiyun * whole. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * a) This library is free software; you can redistribute it and/or 10*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 11*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of the 12*4882a593Smuzhiyun * License, or (at your option) any later version. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * This library is distributed in the hope that it will be useful, 15*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*4882a593Smuzhiyun * GNU General Public License for more details. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * Or, alternatively, 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 22*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 23*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 24*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 25*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 26*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 27*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 28*4882a593Smuzhiyun * conditions: 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 31*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun/* 44*4882a593Smuzhiyun * Device Tree file for Marvell Armada CP110 Master. 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun#include <dt-bindings/comphy/comphy_data.h> 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun/ { 50*4882a593Smuzhiyun cp110-master { 51*4882a593Smuzhiyun #address-cells = <2>; 52*4882a593Smuzhiyun #size-cells = <2>; 53*4882a593Smuzhiyun compatible = "simple-bus"; 54*4882a593Smuzhiyun interrupt-parent = <&gic>; 55*4882a593Smuzhiyun ranges; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun config-space { 58*4882a593Smuzhiyun #address-cells = <1>; 59*4882a593Smuzhiyun #size-cells = <1>; 60*4882a593Smuzhiyun compatible = "simple-bus"; 61*4882a593Smuzhiyun interrupt-parent = <&gic>; 62*4882a593Smuzhiyun ranges = <0x0 0x0 0xf2000000 0x2000000>; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun cpm_ethernet: ethernet@0 { 65*4882a593Smuzhiyun compatible = "marvell,armada-7k-pp22"; 66*4882a593Smuzhiyun reg = <0x0 0x100000>, <0x129000 0xb000>; 67*4882a593Smuzhiyun clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>; 68*4882a593Smuzhiyun clock-names = "pp_clk", "gop_clk", "mg_clk"; 69*4882a593Smuzhiyun status = "disabled"; 70*4882a593Smuzhiyun dma-coherent; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun cpm_eth0: eth0 { 73*4882a593Smuzhiyun interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 74*4882a593Smuzhiyun port-id = <0>; 75*4882a593Smuzhiyun gop-port-id = <0>; 76*4882a593Smuzhiyun status = "disabled"; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun cpm_eth1: eth1 { 80*4882a593Smuzhiyun interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 81*4882a593Smuzhiyun port-id = <1>; 82*4882a593Smuzhiyun gop-port-id = <2>; 83*4882a593Smuzhiyun status = "disabled"; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun cpm_eth2: eth2 { 87*4882a593Smuzhiyun interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 88*4882a593Smuzhiyun port-id = <2>; 89*4882a593Smuzhiyun gop-port-id = <3>; 90*4882a593Smuzhiyun status = "disabled"; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun cpm_mdio: mdio@12a200 { 95*4882a593Smuzhiyun #address-cells = <1>; 96*4882a593Smuzhiyun #size-cells = <0>; 97*4882a593Smuzhiyun compatible = "marvell,orion-mdio"; 98*4882a593Smuzhiyun reg = <0x12a200 0x10>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun cpm_syscon0: system-controller@440000 { 102*4882a593Smuzhiyun compatible = "marvell,cp110-system-controller0", 103*4882a593Smuzhiyun "syscon"; 104*4882a593Smuzhiyun reg = <0x440000 0x1000>; 105*4882a593Smuzhiyun #clock-cells = <2>; 106*4882a593Smuzhiyun core-clock-output-names = 107*4882a593Smuzhiyun "cpm-apll", "cpm-ppv2-core", "cpm-eip", 108*4882a593Smuzhiyun "cpm-core", "cpm-nand-core"; 109*4882a593Smuzhiyun gate-clock-output-names = 110*4882a593Smuzhiyun "cpm-audio", "cpm-communit", "cpm-nand", 111*4882a593Smuzhiyun "cpm-ppv2", "cpm-sdio", "cpm-mg-domain", 112*4882a593Smuzhiyun "cpm-mg-core", "cpm-xor1", "cpm-xor0", 113*4882a593Smuzhiyun "cpm-gop-dp", "none", "cpm-pcie_x10", 114*4882a593Smuzhiyun "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", 115*4882a593Smuzhiyun "cpm-sata", "cpm-sata-usb", "cpm-main", 116*4882a593Smuzhiyun "cpm-sd-mmc", "none", "none", 117*4882a593Smuzhiyun "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1", 118*4882a593Smuzhiyun "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun cpm_pinctl: cpm-pinctl@440000 { 122*4882a593Smuzhiyun compatible = "marvell,mvebu-pinctrl", 123*4882a593Smuzhiyun "marvell,a70x0-pinctrl", 124*4882a593Smuzhiyun "marvell,a80x0-cp0-pinctrl"; 125*4882a593Smuzhiyun bank-name ="cp0-110"; 126*4882a593Smuzhiyun reg = <0x440000 0x20>; 127*4882a593Smuzhiyun pin-count = <63>; 128*4882a593Smuzhiyun max-func = <0xf>; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun cpm_i2c0_pins: cpm-i2c-pins-0 { 131*4882a593Smuzhiyun marvell,pins = < 37 38 >; 132*4882a593Smuzhiyun marvell,function = <2>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun cpm_i2c1_pins: cpm-i2c-pins-1 { 135*4882a593Smuzhiyun marvell,pins = < 35 36 >; 136*4882a593Smuzhiyun marvell,function = <2>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 { 139*4882a593Smuzhiyun marvell,pins = < 44 45 46 47 48 49 50 51 140*4882a593Smuzhiyun 52 53 54 55 >; 141*4882a593Smuzhiyun marvell,function = <1>; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun pca0_pins: cpm-pca0_pins { 144*4882a593Smuzhiyun marvell,pins = <62>; 145*4882a593Smuzhiyun marvell,function = <0>; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun cpm_sdhci_pins: cpm-sdhi-pins-0 { 148*4882a593Smuzhiyun marvell,pins = < 56 57 58 59 60 61 >; 149*4882a593Smuzhiyun marvell,function = <14>; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun cpm_spi0_pins: cpm-spi-pins-0 { 152*4882a593Smuzhiyun marvell,pins = < 13 14 15 16 >; 153*4882a593Smuzhiyun marvell,function = <3>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun cpm_gpio0: gpio@440100 { 158*4882a593Smuzhiyun compatible = "marvell,orion-gpio"; 159*4882a593Smuzhiyun reg = <0x440100 0x40>; 160*4882a593Smuzhiyun ngpios = <32>; 161*4882a593Smuzhiyun gpiobase = <20>; 162*4882a593Smuzhiyun gpio-controller; 163*4882a593Smuzhiyun #gpio-cells = <2>; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun cpm_gpio1: gpio@440140 { 167*4882a593Smuzhiyun compatible = "marvell,orion-gpio"; 168*4882a593Smuzhiyun reg = <0x440140 0x40>; 169*4882a593Smuzhiyun ngpios = <31>; 170*4882a593Smuzhiyun gpiobase = <52>; 171*4882a593Smuzhiyun gpio-controller; 172*4882a593Smuzhiyun #gpio-cells = <2>; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun cpm_sata0: sata@540000 { 176*4882a593Smuzhiyun compatible = "marvell,armada-8k-ahci"; 177*4882a593Smuzhiyun reg = <0x540000 0x30000>; 178*4882a593Smuzhiyun interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 179*4882a593Smuzhiyun clocks = <&cpm_syscon0 1 15>; 180*4882a593Smuzhiyun status = "disabled"; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun cpm_usb3_0: usb3@500000 { 184*4882a593Smuzhiyun compatible = "marvell,armada-8k-xhci", 185*4882a593Smuzhiyun "generic-xhci"; 186*4882a593Smuzhiyun reg = <0x500000 0x4000>; 187*4882a593Smuzhiyun dma-coherent; 188*4882a593Smuzhiyun interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 189*4882a593Smuzhiyun clocks = <&cpm_syscon0 1 22>; 190*4882a593Smuzhiyun status = "disabled"; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun cpm_usb3_1: usb3@510000 { 194*4882a593Smuzhiyun compatible = "marvell,armada-8k-xhci", 195*4882a593Smuzhiyun "generic-xhci"; 196*4882a593Smuzhiyun reg = <0x510000 0x4000>; 197*4882a593Smuzhiyun dma-coherent; 198*4882a593Smuzhiyun interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 199*4882a593Smuzhiyun clocks = <&cpm_syscon0 1 23>; 200*4882a593Smuzhiyun status = "disabled"; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun cpm_spi0: spi@700600 { 204*4882a593Smuzhiyun compatible = "marvell,armada-380-spi"; 205*4882a593Smuzhiyun reg = <0x700600 0x50>; 206*4882a593Smuzhiyun #address-cells = <0x1>; 207*4882a593Smuzhiyun #size-cells = <0x0>; 208*4882a593Smuzhiyun cell-index = <1>; 209*4882a593Smuzhiyun clocks = <&cpm_syscon0 0 3>; 210*4882a593Smuzhiyun status = "disabled"; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun cpm_spi1: spi@700680 { 214*4882a593Smuzhiyun compatible = "marvell,armada-380-spi"; 215*4882a593Smuzhiyun reg = <0x700680 0x50>; 216*4882a593Smuzhiyun #address-cells = <1>; 217*4882a593Smuzhiyun #size-cells = <0>; 218*4882a593Smuzhiyun cell-index = <2>; 219*4882a593Smuzhiyun clocks = <&cpm_syscon0 1 21>; 220*4882a593Smuzhiyun status = "disabled"; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun cpm_i2c0: i2c@701000 { 224*4882a593Smuzhiyun compatible = "marvell,mv78230-i2c"; 225*4882a593Smuzhiyun reg = <0x701000 0x20>; 226*4882a593Smuzhiyun #address-cells = <1>; 227*4882a593Smuzhiyun #size-cells = <0>; 228*4882a593Smuzhiyun interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 229*4882a593Smuzhiyun clocks = <&cpm_syscon0 1 21>; 230*4882a593Smuzhiyun status = "disabled"; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun cpm_i2c1: i2c@701100 { 234*4882a593Smuzhiyun compatible = "marvell,mv78230-i2c"; 235*4882a593Smuzhiyun reg = <0x701100 0x20>; 236*4882a593Smuzhiyun #address-cells = <1>; 237*4882a593Smuzhiyun #size-cells = <0>; 238*4882a593Smuzhiyun interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 239*4882a593Smuzhiyun clocks = <&cpm_syscon0 1 21>; 240*4882a593Smuzhiyun status = "disabled"; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun cpm_comphy: comphy@441000 { 244*4882a593Smuzhiyun compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; 245*4882a593Smuzhiyun reg = <0x441000 0x8>, 246*4882a593Smuzhiyun <0x120000 0x8>; 247*4882a593Smuzhiyun mux-bitcount = <4>; 248*4882a593Smuzhiyun max-lanes = <6>; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun cpm_utmi0: utmi@580000 { 252*4882a593Smuzhiyun compatible = "marvell,mvebu-utmi-2.6.0"; 253*4882a593Smuzhiyun reg = <0x580000 0x1000>, /* utmi-unit */ 254*4882a593Smuzhiyun <0x440420 0x4>, /* usb-cfg */ 255*4882a593Smuzhiyun <0x440440 0x4>; /* utmi-cfg */ 256*4882a593Smuzhiyun utmi-port = <UTMI_PHY_TO_USB3_HOST0>; 257*4882a593Smuzhiyun status = "disabled"; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun cpm_utmi1: utmi@581000 { 261*4882a593Smuzhiyun compatible = "marvell,mvebu-utmi-2.6.0"; 262*4882a593Smuzhiyun reg = <0x581000 0x1000>, /* utmi-unit */ 263*4882a593Smuzhiyun <0x440420 0x4>, /* usb-cfg */ 264*4882a593Smuzhiyun <0x440444 0x4>; /* utmi-cfg */ 265*4882a593Smuzhiyun utmi-port = <UTMI_PHY_TO_USB3_HOST1>; 266*4882a593Smuzhiyun status = "disabled"; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun cpm_sdhci0: sdhci@780000 { 270*4882a593Smuzhiyun compatible = "marvell,armada-8k-sdhci"; 271*4882a593Smuzhiyun reg = <0x780000 0x300>; 272*4882a593Smuzhiyun interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 273*4882a593Smuzhiyun dma-coherent; 274*4882a593Smuzhiyun status = "disabled"; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun cpm_nand: nand@720000 { 278*4882a593Smuzhiyun compatible = "marvell,mvebu-pxa3xx-nand"; 279*4882a593Smuzhiyun reg = <0x720000 0x100>; 280*4882a593Smuzhiyun #address-cells = <1>; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun clocks = <&cpm_syscon0 1 2>; 283*4882a593Smuzhiyun nand-enable-arbiter; 284*4882a593Smuzhiyun num-cs = <1>; 285*4882a593Smuzhiyun nand-ecc-strength = <4>; 286*4882a593Smuzhiyun nand-ecc-step-size = <512>; 287*4882a593Smuzhiyun status = "disabled"; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun cpm_pcie0: pcie@f2600000 { 293*4882a593Smuzhiyun compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 294*4882a593Smuzhiyun reg = <0 0xf2600000 0 0x10000>, 295*4882a593Smuzhiyun <0 0xf6f00000 0 0x80000>; 296*4882a593Smuzhiyun reg-names = "ctrl", "config"; 297*4882a593Smuzhiyun #address-cells = <3>; 298*4882a593Smuzhiyun #size-cells = <2>; 299*4882a593Smuzhiyun #interrupt-cells = <1>; 300*4882a593Smuzhiyun device_type = "pci"; 301*4882a593Smuzhiyun dma-coherent; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun bus-range = <0 0xff>; 304*4882a593Smuzhiyun ranges = 305*4882a593Smuzhiyun /* downstream I/O */ 306*4882a593Smuzhiyun <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 307*4882a593Smuzhiyun /* non-prefetchable memory */ 308*4882a593Smuzhiyun 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; 309*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 310*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 311*4882a593Smuzhiyun interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 312*4882a593Smuzhiyun num-lanes = <1>; 313*4882a593Smuzhiyun clocks = <&cpm_syscon0 1 13>; 314*4882a593Smuzhiyun status = "disabled"; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun cpm_pcie1: pcie@f2620000 { 318*4882a593Smuzhiyun compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 319*4882a593Smuzhiyun reg = <0 0xf2620000 0 0x10000>, 320*4882a593Smuzhiyun <0 0xf7f00000 0 0x80000>; 321*4882a593Smuzhiyun reg-names = "ctrl", "config"; 322*4882a593Smuzhiyun #address-cells = <3>; 323*4882a593Smuzhiyun #size-cells = <2>; 324*4882a593Smuzhiyun #interrupt-cells = <1>; 325*4882a593Smuzhiyun device_type = "pci"; 326*4882a593Smuzhiyun dma-coherent; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun bus-range = <0 0xff>; 329*4882a593Smuzhiyun ranges = 330*4882a593Smuzhiyun /* downstream I/O */ 331*4882a593Smuzhiyun <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000 332*4882a593Smuzhiyun /* non-prefetchable memory */ 333*4882a593Smuzhiyun 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>; 334*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 335*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 336*4882a593Smuzhiyun interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun num-lanes = <1>; 339*4882a593Smuzhiyun clocks = <&cpm_syscon0 1 11>; 340*4882a593Smuzhiyun status = "disabled"; 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun cpm_pcie2: pcie@f2640000 { 344*4882a593Smuzhiyun compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 345*4882a593Smuzhiyun reg = <0 0xf2640000 0 0x10000>, 346*4882a593Smuzhiyun <0 0xf8f00000 0 0x80000>; 347*4882a593Smuzhiyun reg-names = "ctrl", "config"; 348*4882a593Smuzhiyun #address-cells = <3>; 349*4882a593Smuzhiyun #size-cells = <2>; 350*4882a593Smuzhiyun #interrupt-cells = <1>; 351*4882a593Smuzhiyun device_type = "pci"; 352*4882a593Smuzhiyun dma-coherent; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun bus-range = <0 0xff>; 355*4882a593Smuzhiyun ranges = 356*4882a593Smuzhiyun /* downstream I/O */ 357*4882a593Smuzhiyun <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000 358*4882a593Smuzhiyun /* non-prefetchable memory */ 359*4882a593Smuzhiyun 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>; 360*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 361*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 362*4882a593Smuzhiyun interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun num-lanes = <1>; 365*4882a593Smuzhiyun clocks = <&cpm_syscon0 1 12>; 366*4882a593Smuzhiyun status = "disabled"; 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun }; 369*4882a593Smuzhiyun}; 370