1*4882a593Smuzhiyun* Axis ARTPEC-6 PCIe interface 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis PCIe host controller is based on the Synopsys DesignWare PCIe IP 4*4882a593Smuzhiyunand thus inherits all the common properties defined in designware-pcie.txt. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; 8*4882a593Smuzhiyun "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; 9*4882a593Smuzhiyun "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode; 10*4882a593Smuzhiyun "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode; 11*4882a593Smuzhiyun- reg: base addresses and lengths of the PCIe controller (DBI), 12*4882a593Smuzhiyun the PHY controller, and configuration address space. 13*4882a593Smuzhiyun- reg-names: Must include the following entries: 14*4882a593Smuzhiyun - "dbi" 15*4882a593Smuzhiyun - "phy" 16*4882a593Smuzhiyun - "config" 17*4882a593Smuzhiyun- interrupts: A list of interrupt outputs of the controller. Must contain an 18*4882a593Smuzhiyun entry for each entry in the interrupt-names property. 19*4882a593Smuzhiyun- interrupt-names: Must include the following entries: 20*4882a593Smuzhiyun - "msi": The interrupt that is asserted when an MSI is received 21*4882a593Smuzhiyun- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller, 22*4882a593Smuzhiyun used to enable and control the Synopsys IP. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun pcie@f8050000 { 27*4882a593Smuzhiyun compatible = "axis,artpec6-pcie", "snps,dw-pcie"; 28*4882a593Smuzhiyun reg = <0xf8050000 0x2000 29*4882a593Smuzhiyun 0xf8040000 0x1000 30*4882a593Smuzhiyun 0xc0000000 0x2000>; 31*4882a593Smuzhiyun reg-names = "dbi", "phy", "config"; 32*4882a593Smuzhiyun #address-cells = <3>; 33*4882a593Smuzhiyun #size-cells = <2>; 34*4882a593Smuzhiyun device_type = "pci"; 35*4882a593Smuzhiyun /* downstream I/O */ 36*4882a593Smuzhiyun ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 37*4882a593Smuzhiyun /* non-prefetchable memory */ 38*4882a593Smuzhiyun 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; 39*4882a593Smuzhiyun num-lanes = <2>; 40*4882a593Smuzhiyun bus-range = <0x00 0xff>; 41*4882a593Smuzhiyun interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 42*4882a593Smuzhiyun interrupt-names = "msi"; 43*4882a593Smuzhiyun #interrupt-cells = <1>; 44*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0x7>; 45*4882a593Smuzhiyun interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 46*4882a593Smuzhiyun <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 47*4882a593Smuzhiyun <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 48*4882a593Smuzhiyun <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 49*4882a593Smuzhiyun axis,syscon-pcie = <&syscon>; 50*4882a593Smuzhiyun }; 51