1*4882a593Smuzhiyun* Marvell Armada 7K/8K PCIe interface 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis PCIe host controller is based on the Synopsys DesignWare PCIe IP 4*4882a593Smuzhiyunand thus inherits all the common properties defined in designware-pcie.txt. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: "marvell,armada8k-pcie" 8*4882a593Smuzhiyun- reg: must contain two register regions 9*4882a593Smuzhiyun - the control register region 10*4882a593Smuzhiyun - the config space region 11*4882a593Smuzhiyun- reg-names: 12*4882a593Smuzhiyun - "ctrl" for the control register region 13*4882a593Smuzhiyun - "config" for the config space region 14*4882a593Smuzhiyun- interrupts: Interrupt specifier for the PCIe controller 15*4882a593Smuzhiyun- clocks: reference to the PCIe controller clocks 16*4882a593Smuzhiyun- clock-names: mandatory if there is a second clock, in this case the 17*4882a593Smuzhiyun name must be "core" for the first clock and "reg" for the second 18*4882a593Smuzhiyun one 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional properties: 21*4882a593Smuzhiyun- phys: phandle(s) to PHY node(s) following the generic PHY bindings. 22*4882a593Smuzhiyun Either 1, 2 or 4 PHYs might be needed depending on the number of 23*4882a593Smuzhiyun PCIe lanes. 24*4882a593Smuzhiyun- phy-names: names of the PHYs corresponding to the number of lanes. 25*4882a593Smuzhiyun Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for 26*4882a593Smuzhiyun 2 PHYs. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun pcie@f2600000 { 31*4882a593Smuzhiyun compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 32*4882a593Smuzhiyun reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>; 33*4882a593Smuzhiyun reg-names = "ctrl", "config"; 34*4882a593Smuzhiyun #address-cells = <3>; 35*4882a593Smuzhiyun #size-cells = <2>; 36*4882a593Smuzhiyun #interrupt-cells = <1>; 37*4882a593Smuzhiyun device_type = "pci"; 38*4882a593Smuzhiyun dma-coherent; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun bus-range = <0 0xff>; 41*4882a593Smuzhiyun ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */ 42*4882a593Smuzhiyun 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */ 43*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 44*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 45*4882a593Smuzhiyun interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 46*4882a593Smuzhiyun num-lanes = <1>; 47*4882a593Smuzhiyun clocks = <&cpm_syscon0 1 13>; 48*4882a593Smuzhiyun }; 49