xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: PCIe RC controller on Intel Gateway SoCs
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Dilip Kota <eswara.kota@linux.intel.com>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyunselect:
13*4882a593Smuzhiyun  properties:
14*4882a593Smuzhiyun    compatible:
15*4882a593Smuzhiyun      contains:
16*4882a593Smuzhiyun        const: intel,lgm-pcie
17*4882a593Smuzhiyun  required:
18*4882a593Smuzhiyun    - compatible
19*4882a593Smuzhiyun
20*4882a593Smuzhiyunproperties:
21*4882a593Smuzhiyun  compatible:
22*4882a593Smuzhiyun    items:
23*4882a593Smuzhiyun      - const: intel,lgm-pcie
24*4882a593Smuzhiyun      - const: snps,dw-pcie
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun  device_type:
27*4882a593Smuzhiyun    const: pci
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun  "#address-cells":
30*4882a593Smuzhiyun    const: 3
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun  "#size-cells":
33*4882a593Smuzhiyun    const: 2
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun  reg:
36*4882a593Smuzhiyun    items:
37*4882a593Smuzhiyun      - description: Controller control and status registers.
38*4882a593Smuzhiyun      - description: PCIe configuration registers.
39*4882a593Smuzhiyun      - description: Controller application registers.
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun  reg-names:
42*4882a593Smuzhiyun    items:
43*4882a593Smuzhiyun      - const: dbi
44*4882a593Smuzhiyun      - const: config
45*4882a593Smuzhiyun      - const: app
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun  ranges:
48*4882a593Smuzhiyun    maxItems: 1
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun  resets:
51*4882a593Smuzhiyun    maxItems: 1
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun  clocks:
54*4882a593Smuzhiyun    maxItems: 1
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun  phys:
57*4882a593Smuzhiyun    maxItems: 1
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun  phy-names:
60*4882a593Smuzhiyun    const: pcie
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun  reset-gpios:
63*4882a593Smuzhiyun    maxItems: 1
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun  linux,pci-domain: true
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun  num-lanes:
68*4882a593Smuzhiyun    maximum: 2
69*4882a593Smuzhiyun    description: Number of lanes to use for this port.
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun  '#interrupt-cells':
72*4882a593Smuzhiyun    const: 1
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun  interrupt-map-mask:
75*4882a593Smuzhiyun    description: Standard PCI IRQ mapping properties.
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun  interrupt-map:
78*4882a593Smuzhiyun    description: Standard PCI IRQ mapping properties.
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun  max-link-speed:
81*4882a593Smuzhiyun    description: Specify PCI Gen for link capability.
82*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
83*4882a593Smuzhiyun    enum: [1, 2, 3, 4]
84*4882a593Smuzhiyun    default: 1
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun  bus-range:
87*4882a593Smuzhiyun    description: Range of bus numbers associated with this controller.
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun  reset-assert-ms:
90*4882a593Smuzhiyun    description: |
91*4882a593Smuzhiyun      Delay after asserting reset to the PCIe device.
92*4882a593Smuzhiyun    maximum: 500
93*4882a593Smuzhiyun    default: 100
94*4882a593Smuzhiyun
95*4882a593Smuzhiyunrequired:
96*4882a593Smuzhiyun  - compatible
97*4882a593Smuzhiyun  - device_type
98*4882a593Smuzhiyun  - "#address-cells"
99*4882a593Smuzhiyun  - "#size-cells"
100*4882a593Smuzhiyun  - reg
101*4882a593Smuzhiyun  - reg-names
102*4882a593Smuzhiyun  - ranges
103*4882a593Smuzhiyun  - resets
104*4882a593Smuzhiyun  - clocks
105*4882a593Smuzhiyun  - phys
106*4882a593Smuzhiyun  - phy-names
107*4882a593Smuzhiyun  - reset-gpios
108*4882a593Smuzhiyun  - '#interrupt-cells'
109*4882a593Smuzhiyun  - interrupt-map
110*4882a593Smuzhiyun  - interrupt-map-mask
111*4882a593Smuzhiyun
112*4882a593SmuzhiyunadditionalProperties: false
113*4882a593Smuzhiyun
114*4882a593Smuzhiyunexamples:
115*4882a593Smuzhiyun  - |
116*4882a593Smuzhiyun    #include <dt-bindings/gpio/gpio.h>
117*4882a593Smuzhiyun    pcie10: pcie@d0e00000 {
118*4882a593Smuzhiyun      compatible = "intel,lgm-pcie", "snps,dw-pcie";
119*4882a593Smuzhiyun      device_type = "pci";
120*4882a593Smuzhiyun      #address-cells = <3>;
121*4882a593Smuzhiyun      #size-cells = <2>;
122*4882a593Smuzhiyun      reg = <0xd0e00000 0x1000>,
123*4882a593Smuzhiyun            <0xd2000000 0x800000>,
124*4882a593Smuzhiyun            <0xd0a41000 0x1000>;
125*4882a593Smuzhiyun      reg-names = "dbi", "config", "app";
126*4882a593Smuzhiyun      linux,pci-domain = <0>;
127*4882a593Smuzhiyun      max-link-speed = <4>;
128*4882a593Smuzhiyun      bus-range = <0x00 0x08>;
129*4882a593Smuzhiyun      #interrupt-cells = <1>;
130*4882a593Smuzhiyun      interrupt-map-mask = <0 0 0 0x7>;
131*4882a593Smuzhiyun      interrupt-map = <0 0 0 1 &ioapic1 27 1>,
132*4882a593Smuzhiyun                      <0 0 0 2 &ioapic1 28 1>,
133*4882a593Smuzhiyun                      <0 0 0 3 &ioapic1 29 1>,
134*4882a593Smuzhiyun                      <0 0 0 4 &ioapic1 30 1>;
135*4882a593Smuzhiyun      ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
136*4882a593Smuzhiyun      resets = <&rcu0 0x50 0>;
137*4882a593Smuzhiyun      clocks = <&cgu0 120>;
138*4882a593Smuzhiyun      phys = <&cb0phy0>;
139*4882a593Smuzhiyun      phy-names = "pcie";
140*4882a593Smuzhiyun      reset-assert-ms = <500>;
141*4882a593Smuzhiyun      reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
142*4882a593Smuzhiyun      num-lanes = <2>;
143*4882a593Smuzhiyun    };
144