1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * DTS file for all SPEAr1310 SoCs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2012 Viresh Kumar <vireshk@kernel.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/include/ "spear13xx.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun compatible = "st,spear1310"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun ahb { 14*4882a593Smuzhiyun spics: spics@e0700000{ 15*4882a593Smuzhiyun compatible = "st,spear-spics-gpio"; 16*4882a593Smuzhiyun reg = <0xe0700000 0x1000>; 17*4882a593Smuzhiyun st-spics,peripcfg-reg = <0x3b0>; 18*4882a593Smuzhiyun st-spics,sw-enable-bit = <12>; 19*4882a593Smuzhiyun st-spics,cs-value-bit = <11>; 20*4882a593Smuzhiyun st-spics,cs-enable-mask = <3>; 21*4882a593Smuzhiyun st-spics,cs-enable-shift = <8>; 22*4882a593Smuzhiyun gpio-controller; 23*4882a593Smuzhiyun #gpio-cells = <2>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun miphy0: miphy@eb800000 { 27*4882a593Smuzhiyun compatible = "st,spear1310-miphy"; 28*4882a593Smuzhiyun reg = <0xeb800000 0x4000>; 29*4882a593Smuzhiyun misc = <&misc>; 30*4882a593Smuzhiyun phy-id = <0>; 31*4882a593Smuzhiyun #phy-cells = <1>; 32*4882a593Smuzhiyun status = "disabled"; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun miphy1: miphy@eb804000 { 36*4882a593Smuzhiyun compatible = "st,spear1310-miphy"; 37*4882a593Smuzhiyun reg = <0xeb804000 0x4000>; 38*4882a593Smuzhiyun misc = <&misc>; 39*4882a593Smuzhiyun phy-id = <1>; 40*4882a593Smuzhiyun #phy-cells = <1>; 41*4882a593Smuzhiyun status = "disabled"; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun miphy2: miphy@eb808000 { 45*4882a593Smuzhiyun compatible = "st,spear1310-miphy"; 46*4882a593Smuzhiyun reg = <0xeb808000 0x4000>; 47*4882a593Smuzhiyun misc = <&misc>; 48*4882a593Smuzhiyun phy-id = <2>; 49*4882a593Smuzhiyun #phy-cells = <1>; 50*4882a593Smuzhiyun status = "disabled"; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun ahci0: ahci@b1000000 { 54*4882a593Smuzhiyun compatible = "snps,spear-ahci"; 55*4882a593Smuzhiyun reg = <0xb1000000 0x10000>; 56*4882a593Smuzhiyun interrupts = <0 68 0x4>; 57*4882a593Smuzhiyun phys = <&miphy0 0>; 58*4882a593Smuzhiyun phy-names = "sata-phy"; 59*4882a593Smuzhiyun status = "disabled"; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun ahci1: ahci@b1800000 { 63*4882a593Smuzhiyun compatible = "snps,spear-ahci"; 64*4882a593Smuzhiyun reg = <0xb1800000 0x10000>; 65*4882a593Smuzhiyun interrupts = <0 69 0x4>; 66*4882a593Smuzhiyun phys = <&miphy1 0>; 67*4882a593Smuzhiyun phy-names = "sata-phy"; 68*4882a593Smuzhiyun status = "disabled"; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun ahci2: ahci@b4000000 { 72*4882a593Smuzhiyun compatible = "snps,spear-ahci"; 73*4882a593Smuzhiyun reg = <0xb4000000 0x10000>; 74*4882a593Smuzhiyun interrupts = <0 70 0x4>; 75*4882a593Smuzhiyun phys = <&miphy2 0>; 76*4882a593Smuzhiyun phy-names = "sata-phy"; 77*4882a593Smuzhiyun status = "disabled"; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun pcie0: pcie@b1000000 { 81*4882a593Smuzhiyun compatible = "st,spear1340-pcie", "snps,dw-pcie"; 82*4882a593Smuzhiyun reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; 83*4882a593Smuzhiyun reg-names = "dbi", "config"; 84*4882a593Smuzhiyun interrupts = <0 68 0x4>; 85*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 86*4882a593Smuzhiyun interrupt-map = <0x0 0 &gic 0 68 0x4>; 87*4882a593Smuzhiyun num-lanes = <1>; 88*4882a593Smuzhiyun phys = <&miphy0 1>; 89*4882a593Smuzhiyun phy-names = "pcie-phy"; 90*4882a593Smuzhiyun #address-cells = <3>; 91*4882a593Smuzhiyun #size-cells = <2>; 92*4882a593Smuzhiyun device_type = "pci"; 93*4882a593Smuzhiyun ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ 94*4882a593Smuzhiyun 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ 95*4882a593Smuzhiyun bus-range = <0x00 0xff>; 96*4882a593Smuzhiyun status = "disabled"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun pcie1: pcie@b1800000 { 100*4882a593Smuzhiyun compatible = "st,spear1340-pcie", "snps,dw-pcie"; 101*4882a593Smuzhiyun reg = <0xb1800000 0x4000>, <0x90000000 0x20000>; 102*4882a593Smuzhiyun reg-names = "dbi", "config"; 103*4882a593Smuzhiyun interrupts = <0 69 0x4>; 104*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 105*4882a593Smuzhiyun interrupt-map = <0x0 0 &gic 0 69 0x4>; 106*4882a593Smuzhiyun num-lanes = <1>; 107*4882a593Smuzhiyun phys = <&miphy1 1>; 108*4882a593Smuzhiyun phy-names = "pcie-phy"; 109*4882a593Smuzhiyun #address-cells = <3>; 110*4882a593Smuzhiyun #size-cells = <2>; 111*4882a593Smuzhiyun device_type = "pci"; 112*4882a593Smuzhiyun ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ 113*4882a593Smuzhiyun 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ 114*4882a593Smuzhiyun bus-range = <0x00 0xff>; 115*4882a593Smuzhiyun status = "disabled"; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun pcie2: pcie@b4000000 { 119*4882a593Smuzhiyun compatible = "st,spear1340-pcie", "snps,dw-pcie"; 120*4882a593Smuzhiyun reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>; 121*4882a593Smuzhiyun reg-names = "dbi", "config"; 122*4882a593Smuzhiyun interrupts = <0 70 0x4>; 123*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 124*4882a593Smuzhiyun interrupt-map = <0x0 0 &gic 0 70 0x4>; 125*4882a593Smuzhiyun num-lanes = <1>; 126*4882a593Smuzhiyun phys = <&miphy2 1>; 127*4882a593Smuzhiyun phy-names = "pcie-phy"; 128*4882a593Smuzhiyun #address-cells = <3>; 129*4882a593Smuzhiyun #size-cells = <2>; 130*4882a593Smuzhiyun device_type = "pci"; 131*4882a593Smuzhiyun ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ 132*4882a593Smuzhiyun 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ 133*4882a593Smuzhiyun bus-range = <0x00 0xff>; 134*4882a593Smuzhiyun status = "disabled"; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun gmac1: eth@5c400000 { 138*4882a593Smuzhiyun compatible = "st,spear600-gmac"; 139*4882a593Smuzhiyun reg = <0x5c400000 0x8000>; 140*4882a593Smuzhiyun interrupts = <0 95 0x4>; 141*4882a593Smuzhiyun interrupt-names = "macirq"; 142*4882a593Smuzhiyun phy-mode = "mii"; 143*4882a593Smuzhiyun status = "disabled"; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun gmac2: eth@5c500000 { 147*4882a593Smuzhiyun compatible = "st,spear600-gmac"; 148*4882a593Smuzhiyun reg = <0x5c500000 0x8000>; 149*4882a593Smuzhiyun interrupts = <0 96 0x4>; 150*4882a593Smuzhiyun interrupt-names = "macirq"; 151*4882a593Smuzhiyun phy-mode = "mii"; 152*4882a593Smuzhiyun status = "disabled"; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun gmac3: eth@5c600000 { 156*4882a593Smuzhiyun compatible = "st,spear600-gmac"; 157*4882a593Smuzhiyun reg = <0x5c600000 0x8000>; 158*4882a593Smuzhiyun interrupts = <0 97 0x4>; 159*4882a593Smuzhiyun interrupt-names = "macirq"; 160*4882a593Smuzhiyun phy-mode = "rmii"; 161*4882a593Smuzhiyun status = "disabled"; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun gmac4: eth@5c700000 { 165*4882a593Smuzhiyun compatible = "st,spear600-gmac"; 166*4882a593Smuzhiyun reg = <0x5c700000 0x8000>; 167*4882a593Smuzhiyun interrupts = <0 98 0x4>; 168*4882a593Smuzhiyun interrupt-names = "macirq"; 169*4882a593Smuzhiyun phy-mode = "rgmii"; 170*4882a593Smuzhiyun status = "disabled"; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun pinmux: pinmux@e0700000 { 174*4882a593Smuzhiyun compatible = "st,spear1310-pinmux"; 175*4882a593Smuzhiyun reg = <0xe0700000 0x1000>; 176*4882a593Smuzhiyun #gpio-range-cells = <3>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun apb { 180*4882a593Smuzhiyun i2c1: i2c@5cd00000 { 181*4882a593Smuzhiyun #address-cells = <1>; 182*4882a593Smuzhiyun #size-cells = <0>; 183*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 184*4882a593Smuzhiyun reg = <0x5cd00000 0x1000>; 185*4882a593Smuzhiyun interrupts = <0 87 0x4>; 186*4882a593Smuzhiyun status = "disabled"; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun i2c2: i2c@5ce00000 { 190*4882a593Smuzhiyun #address-cells = <1>; 191*4882a593Smuzhiyun #size-cells = <0>; 192*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 193*4882a593Smuzhiyun reg = <0x5ce00000 0x1000>; 194*4882a593Smuzhiyun interrupts = <0 88 0x4>; 195*4882a593Smuzhiyun status = "disabled"; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun i2c3: i2c@5cf00000 { 199*4882a593Smuzhiyun #address-cells = <1>; 200*4882a593Smuzhiyun #size-cells = <0>; 201*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 202*4882a593Smuzhiyun reg = <0x5cf00000 0x1000>; 203*4882a593Smuzhiyun interrupts = <0 89 0x4>; 204*4882a593Smuzhiyun status = "disabled"; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun i2c4: i2c@5d000000 { 208*4882a593Smuzhiyun #address-cells = <1>; 209*4882a593Smuzhiyun #size-cells = <0>; 210*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 211*4882a593Smuzhiyun reg = <0x5d000000 0x1000>; 212*4882a593Smuzhiyun interrupts = <0 90 0x4>; 213*4882a593Smuzhiyun status = "disabled"; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun i2c5: i2c@5d100000 { 217*4882a593Smuzhiyun #address-cells = <1>; 218*4882a593Smuzhiyun #size-cells = <0>; 219*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 220*4882a593Smuzhiyun reg = <0x5d100000 0x1000>; 221*4882a593Smuzhiyun interrupts = <0 91 0x4>; 222*4882a593Smuzhiyun status = "disabled"; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun i2c6: i2c@5d200000 { 226*4882a593Smuzhiyun #address-cells = <1>; 227*4882a593Smuzhiyun #size-cells = <0>; 228*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 229*4882a593Smuzhiyun reg = <0x5d200000 0x1000>; 230*4882a593Smuzhiyun interrupts = <0 92 0x4>; 231*4882a593Smuzhiyun status = "disabled"; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun i2c7: i2c@5d300000 { 235*4882a593Smuzhiyun #address-cells = <1>; 236*4882a593Smuzhiyun #size-cells = <0>; 237*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 238*4882a593Smuzhiyun reg = <0x5d300000 0x1000>; 239*4882a593Smuzhiyun interrupts = <0 93 0x4>; 240*4882a593Smuzhiyun status = "disabled"; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun spi1: spi@5d400000 { 244*4882a593Smuzhiyun compatible = "arm,pl022", "arm,primecell"; 245*4882a593Smuzhiyun reg = <0x5d400000 0x1000>; 246*4882a593Smuzhiyun interrupts = <0 99 0x4>; 247*4882a593Smuzhiyun #address-cells = <1>; 248*4882a593Smuzhiyun #size-cells = <0>; 249*4882a593Smuzhiyun status = "disabled"; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun serial@5c800000 { 253*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 254*4882a593Smuzhiyun reg = <0x5c800000 0x1000>; 255*4882a593Smuzhiyun interrupts = <0 82 0x4>; 256*4882a593Smuzhiyun status = "disabled"; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun serial@5c900000 { 260*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 261*4882a593Smuzhiyun reg = <0x5c900000 0x1000>; 262*4882a593Smuzhiyun interrupts = <0 83 0x4>; 263*4882a593Smuzhiyun status = "disabled"; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun serial@5ca00000 { 267*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 268*4882a593Smuzhiyun reg = <0x5ca00000 0x1000>; 269*4882a593Smuzhiyun interrupts = <0 84 0x4>; 270*4882a593Smuzhiyun status = "disabled"; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun serial@5cb00000 { 274*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 275*4882a593Smuzhiyun reg = <0x5cb00000 0x1000>; 276*4882a593Smuzhiyun interrupts = <0 85 0x4>; 277*4882a593Smuzhiyun status = "disabled"; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun serial@5cc00000 { 281*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 282*4882a593Smuzhiyun reg = <0x5cc00000 0x1000>; 283*4882a593Smuzhiyun interrupts = <0 86 0x4>; 284*4882a593Smuzhiyun status = "disabled"; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun thermal@e07008c4 { 288*4882a593Smuzhiyun st,thermal-flags = <0x7000>; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun gpiopinctrl: gpio@d8400000 { 292*4882a593Smuzhiyun compatible = "st,spear-plgpio"; 293*4882a593Smuzhiyun reg = <0xd8400000 0x1000>; 294*4882a593Smuzhiyun interrupts = <0 100 0x4>; 295*4882a593Smuzhiyun #interrupt-cells = <1>; 296*4882a593Smuzhiyun interrupt-controller; 297*4882a593Smuzhiyun gpio-controller; 298*4882a593Smuzhiyun #gpio-cells = <2>; 299*4882a593Smuzhiyun gpio-ranges = <&pinmux 0 0 246>; 300*4882a593Smuzhiyun status = "disabled"; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun st-plgpio,ngpio = <246>; 303*4882a593Smuzhiyun st-plgpio,enb-reg = <0xd0>; 304*4882a593Smuzhiyun st-plgpio,wdata-reg = <0x90>; 305*4882a593Smuzhiyun st-plgpio,dir-reg = <0xb0>; 306*4882a593Smuzhiyun st-plgpio,ie-reg = <0x30>; 307*4882a593Smuzhiyun st-plgpio,rdata-reg = <0x70>; 308*4882a593Smuzhiyun st-plgpio,mis-reg = <0x10>; 309*4882a593Smuzhiyun st-plgpio,eit-reg = <0x50>; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun}; 314