1*4882a593SmuzhiyunArmada-8K PCIe DT details: 2*4882a593Smuzhiyun========================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunArmada-8k uses synopsis designware PCIe controller. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie". 8*4882a593Smuzhiyun- reg: base addresses and lengths of the pcie control and global control registers. 9*4882a593Smuzhiyun "ctrl" registers points to the global control registers, while the "config" space 10*4882a593Smuzhiyun points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below. 11*4882a593Smuzhiyun- interrupt-map-mask and interrupt-map, standard PCI properties to 12*4882a593Smuzhiyun define the mapping of the PCIe interface to interrupt numbers. 13*4882a593Smuzhiyun- All other definitions as per generic PCI bindings 14*4882a593SmuzhiyunSee Linux kernel documentation: 15*4882a593Smuzhiyun"Documentation/devicetree/bindings/pci/designware-pcie.txt" 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593SmuzhiyunPHY support is still not supported for armada-8k, once it will, the following parameters can be used: 19*4882a593Smuzhiyun- phys : phandle to phy node associated with pcie controller. 20*4882a593Smuzhiyun- phy-names : must be "pcie-phy" 21*4882a593Smuzhiyun- marvell,reset-gpio : specifies a gpio that needs to be activated for plug-in 22*4882a593Smuzhiyun card reset signal release. 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyuncpm_pcie0: pcie@f2600000 { 26*4882a593Smuzhiyun compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 27*4882a593Smuzhiyun reg = <0 0xf2600000 0 0x10000>, 28*4882a593Smuzhiyun <0 0xf6f00000 0 0x80000>; 29*4882a593Smuzhiyun reg-names = "ctrl", "config"; 30*4882a593Smuzhiyun #address-cells = <3>; 31*4882a593Smuzhiyun #size-cells = <2>; 32*4882a593Smuzhiyun #interrupt-cells = <1>; 33*4882a593Smuzhiyun device_type = "pci"; 34*4882a593Smuzhiyun dma-coherent; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun bus-range = <0 0xff>; 37*4882a593Smuzhiyun ranges = 38*4882a593Smuzhiyun /* downstream I/O */ 39*4882a593Smuzhiyun <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 40*4882a593Smuzhiyun /* non-prefetchable memory */ 41*4882a593Smuzhiyun 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; 42*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 43*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 44*4882a593Smuzhiyun interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 45*4882a593Smuzhiyun num-lanes = <1>; 46*4882a593Smuzhiyun clocks = <&cpm_syscon0 1 13>; 47*4882a593Smuzhiyun marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; 48*4882a593Smuzhiyun status = "disabled"; 49*4882a593Smuzhiyun}; 50