1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593Smuzhiyunmenu "DesignWare PCI Core Support" 4*4882a593Smuzhiyun depends on PCI 5*4882a593Smuzhiyun 6*4882a593Smuzhiyunconfig PCIE_DW 7*4882a593Smuzhiyun bool 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunconfig PCIE_DW_HOST 10*4882a593Smuzhiyun bool 11*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 12*4882a593Smuzhiyun select PCIE_DW 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunconfig PCIE_DW_EP 15*4882a593Smuzhiyun bool 16*4882a593Smuzhiyun depends on PCI_ENDPOINT 17*4882a593Smuzhiyun select PCIE_DW 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunconfig PCI_DRA7XX 20*4882a593Smuzhiyun bool 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunconfig PCI_DRA7XX_HOST 23*4882a593Smuzhiyun bool "TI DRA7xx PCIe controller Host Mode" 24*4882a593Smuzhiyun depends on SOC_DRA7XX || COMPILE_TEST 25*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 26*4882a593Smuzhiyun depends on OF && HAS_IOMEM && TI_PIPE3 27*4882a593Smuzhiyun select PCIE_DW_HOST 28*4882a593Smuzhiyun select PCI_DRA7XX 29*4882a593Smuzhiyun default y if SOC_DRA7XX 30*4882a593Smuzhiyun help 31*4882a593Smuzhiyun Enables support for the PCIe controller in the DRA7xx SoC to work in 32*4882a593Smuzhiyun host mode. There are two instances of PCIe controller in DRA7xx. 33*4882a593Smuzhiyun This controller can work either as EP or RC. In order to enable 34*4882a593Smuzhiyun host-specific features PCI_DRA7XX_HOST must be selected and in order 35*4882a593Smuzhiyun to enable device-specific features PCI_DRA7XX_EP must be selected. 36*4882a593Smuzhiyun This uses the DesignWare core. 37*4882a593Smuzhiyun 38*4882a593Smuzhiyunconfig PCI_DRA7XX_EP 39*4882a593Smuzhiyun bool "TI DRA7xx PCIe controller Endpoint Mode" 40*4882a593Smuzhiyun depends on SOC_DRA7XX || COMPILE_TEST 41*4882a593Smuzhiyun depends on PCI_ENDPOINT 42*4882a593Smuzhiyun depends on OF && HAS_IOMEM && TI_PIPE3 43*4882a593Smuzhiyun select PCIE_DW_EP 44*4882a593Smuzhiyun select PCI_DRA7XX 45*4882a593Smuzhiyun help 46*4882a593Smuzhiyun Enables support for the PCIe controller in the DRA7xx SoC to work in 47*4882a593Smuzhiyun endpoint mode. There are two instances of PCIe controller in DRA7xx. 48*4882a593Smuzhiyun This controller can work either as EP or RC. In order to enable 49*4882a593Smuzhiyun host-specific features PCI_DRA7XX_HOST must be selected and in order 50*4882a593Smuzhiyun to enable device-specific features PCI_DRA7XX_EP must be selected. 51*4882a593Smuzhiyun This uses the DesignWare core. 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunconfig PCIE_DW_PLAT 54*4882a593Smuzhiyun bool 55*4882a593Smuzhiyun 56*4882a593Smuzhiyunconfig PCIE_DW_PLAT_HOST 57*4882a593Smuzhiyun bool "Platform bus based DesignWare PCIe Controller - Host mode" 58*4882a593Smuzhiyun depends on PCI && PCI_MSI_IRQ_DOMAIN 59*4882a593Smuzhiyun select PCIE_DW_HOST 60*4882a593Smuzhiyun select PCIE_DW_PLAT 61*4882a593Smuzhiyun help 62*4882a593Smuzhiyun Enables support for the PCIe controller in the Designware IP to 63*4882a593Smuzhiyun work in host mode. There are two instances of PCIe controller in 64*4882a593Smuzhiyun Designware IP. 65*4882a593Smuzhiyun This controller can work either as EP or RC. In order to enable 66*4882a593Smuzhiyun host-specific features PCIE_DW_PLAT_HOST must be selected and in 67*4882a593Smuzhiyun order to enable device-specific features PCI_DW_PLAT_EP must be 68*4882a593Smuzhiyun selected. 69*4882a593Smuzhiyun 70*4882a593Smuzhiyunconfig PCIE_DW_PLAT_EP 71*4882a593Smuzhiyun bool "Platform bus based DesignWare PCIe Controller - Endpoint mode" 72*4882a593Smuzhiyun depends on PCI && PCI_MSI_IRQ_DOMAIN 73*4882a593Smuzhiyun depends on PCI_ENDPOINT 74*4882a593Smuzhiyun select PCIE_DW_EP 75*4882a593Smuzhiyun select PCIE_DW_PLAT 76*4882a593Smuzhiyun help 77*4882a593Smuzhiyun Enables support for the PCIe controller in the Designware IP to 78*4882a593Smuzhiyun work in endpoint mode. There are two instances of PCIe controller 79*4882a593Smuzhiyun in Designware IP. 80*4882a593Smuzhiyun This controller can work either as EP or RC. In order to enable 81*4882a593Smuzhiyun host-specific features PCIE_DW_PLAT_HOST must be selected and in 82*4882a593Smuzhiyun order to enable device-specific features PCI_DW_PLAT_EP must be 83*4882a593Smuzhiyun selected. 84*4882a593Smuzhiyun 85*4882a593Smuzhiyunconfig PCIE_DW_ROCKCHIP 86*4882a593Smuzhiyun tristate "Rockchip DesignWare PCIe controller" 87*4882a593Smuzhiyun select PCIE_DW 88*4882a593Smuzhiyun select PCIE_DW_HOST 89*4882a593Smuzhiyun depends on ARCH_ROCKCHIP 90*4882a593Smuzhiyun depends on OF 91*4882a593Smuzhiyun help 92*4882a593Smuzhiyun Enables support for the DW PCIe controller in the Rockchip SoC. 93*4882a593Smuzhiyun 94*4882a593Smuzhiyunconfig PCIE_RK_THREADED_INIT 95*4882a593Smuzhiyun bool "Threaded initialize Rockchip DW based PCIe controller" 96*4882a593Smuzhiyun depends on PCIE_DW_ROCKCHIP 97*4882a593Smuzhiyun default y 98*4882a593Smuzhiyun help 99*4882a593Smuzhiyun Enables threaded initialize Rockchip DW based PCIe controller. 100*4882a593Smuzhiyun 101*4882a593Smuzhiyunconfig PCIE_DW_DMATEST 102*4882a593Smuzhiyun bool "DesignWare PCIe DMA test" 103*4882a593Smuzhiyun depends on PCIE_DW_ROCKCHIP 104*4882a593Smuzhiyun depends on !ROCKCHIP_PCIE_DMA_OBJ 105*4882a593Smuzhiyun help 106*4882a593Smuzhiyun Enables support for the DW PCIe controller DMA test. 107*4882a593Smuzhiyun 108*4882a593Smuzhiyunconfig PCIE_DW_ROCKCHIP_EP 109*4882a593Smuzhiyun bool "Rockchip DesignWare PCIe EP controller" 110*4882a593Smuzhiyun select PCIE_DW 111*4882a593Smuzhiyun depends on ARCH_ROCKCHIP 112*4882a593Smuzhiyun depends on OF 113*4882a593Smuzhiyun help 114*4882a593Smuzhiyun Enables support for the DW PCIe controller in the Rockchip SoC. 115*4882a593Smuzhiyun 116*4882a593Smuzhiyunconfig PCI_EXYNOS 117*4882a593Smuzhiyun bool "Samsung Exynos PCIe controller" 118*4882a593Smuzhiyun depends on SOC_EXYNOS5440 || COMPILE_TEST 119*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 120*4882a593Smuzhiyun select PCIE_DW_HOST 121*4882a593Smuzhiyun 122*4882a593Smuzhiyunconfig PCI_IMX6 123*4882a593Smuzhiyun bool "Freescale i.MX6/7/8 PCIe controller" 124*4882a593Smuzhiyun depends on ARCH_MXC || COMPILE_TEST 125*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 126*4882a593Smuzhiyun select PCIE_DW_HOST 127*4882a593Smuzhiyun 128*4882a593Smuzhiyunconfig PCIE_SPEAR13XX 129*4882a593Smuzhiyun bool "STMicroelectronics SPEAr PCIe controller" 130*4882a593Smuzhiyun depends on ARCH_SPEAR13XX || COMPILE_TEST 131*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 132*4882a593Smuzhiyun select PCIE_DW_HOST 133*4882a593Smuzhiyun help 134*4882a593Smuzhiyun Say Y here if you want PCIe support on SPEAr13XX SoCs. 135*4882a593Smuzhiyun 136*4882a593Smuzhiyunconfig PCI_KEYSTONE 137*4882a593Smuzhiyun bool 138*4882a593Smuzhiyun 139*4882a593Smuzhiyunconfig PCI_KEYSTONE_HOST 140*4882a593Smuzhiyun bool "PCI Keystone Host Mode" 141*4882a593Smuzhiyun depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) 142*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 143*4882a593Smuzhiyun select PCIE_DW_HOST 144*4882a593Smuzhiyun select PCI_KEYSTONE 145*4882a593Smuzhiyun help 146*4882a593Smuzhiyun Enables support for the PCIe controller in the Keystone SoC to 147*4882a593Smuzhiyun work in host mode. The PCI controller on Keystone is based on 148*4882a593Smuzhiyun DesignWare hardware and therefore the driver re-uses the 149*4882a593Smuzhiyun DesignWare core functions to implement the driver. 150*4882a593Smuzhiyun 151*4882a593Smuzhiyunconfig PCI_KEYSTONE_EP 152*4882a593Smuzhiyun bool "PCI Keystone Endpoint Mode" 153*4882a593Smuzhiyun depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) 154*4882a593Smuzhiyun depends on PCI_ENDPOINT 155*4882a593Smuzhiyun select PCIE_DW_EP 156*4882a593Smuzhiyun select PCI_KEYSTONE 157*4882a593Smuzhiyun help 158*4882a593Smuzhiyun Enables support for the PCIe controller in the Keystone SoC to 159*4882a593Smuzhiyun work in endpoint mode. The PCI controller on Keystone is based 160*4882a593Smuzhiyun on DesignWare hardware and therefore the driver re-uses the 161*4882a593Smuzhiyun DesignWare core functions to implement the driver. 162*4882a593Smuzhiyun 163*4882a593Smuzhiyunconfig PCI_LAYERSCAPE 164*4882a593Smuzhiyun bool "Freescale Layerscape PCIe controller - Host mode" 165*4882a593Smuzhiyun depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) 166*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 167*4882a593Smuzhiyun select MFD_SYSCON 168*4882a593Smuzhiyun select PCIE_DW_HOST 169*4882a593Smuzhiyun help 170*4882a593Smuzhiyun Say Y here if you want to enable PCIe controller support on Layerscape 171*4882a593Smuzhiyun SoCs to work in Host mode. 172*4882a593Smuzhiyun This controller can work either as EP or RC. The RCW[HOST_AGT_PEX] 173*4882a593Smuzhiyun determines which PCIe controller works in EP mode and which PCIe 174*4882a593Smuzhiyun controller works in RC mode. 175*4882a593Smuzhiyun 176*4882a593Smuzhiyunconfig PCI_LAYERSCAPE_EP 177*4882a593Smuzhiyun bool "Freescale Layerscape PCIe controller - Endpoint mode" 178*4882a593Smuzhiyun depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) 179*4882a593Smuzhiyun depends on PCI_ENDPOINT 180*4882a593Smuzhiyun select PCIE_DW_EP 181*4882a593Smuzhiyun help 182*4882a593Smuzhiyun Say Y here if you want to enable PCIe controller support on Layerscape 183*4882a593Smuzhiyun SoCs to work in Endpoint mode. 184*4882a593Smuzhiyun This controller can work either as EP or RC. The RCW[HOST_AGT_PEX] 185*4882a593Smuzhiyun determines which PCIe controller works in EP mode and which PCIe 186*4882a593Smuzhiyun controller works in RC mode. 187*4882a593Smuzhiyun 188*4882a593Smuzhiyunconfig PCI_HISI 189*4882a593Smuzhiyun depends on OF && (ARM64 || COMPILE_TEST) 190*4882a593Smuzhiyun bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers" 191*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 192*4882a593Smuzhiyun select PCIE_DW_HOST 193*4882a593Smuzhiyun select PCI_HOST_COMMON 194*4882a593Smuzhiyun help 195*4882a593Smuzhiyun Say Y here if you want PCIe controller support on HiSilicon 196*4882a593Smuzhiyun Hip05 and Hip06 SoCs 197*4882a593Smuzhiyun 198*4882a593Smuzhiyunconfig PCIE_QCOM 199*4882a593Smuzhiyun bool "Qualcomm PCIe controller" 200*4882a593Smuzhiyun depends on OF && (ARCH_QCOM || COMPILE_TEST) 201*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 202*4882a593Smuzhiyun select PCIE_DW_HOST 203*4882a593Smuzhiyun help 204*4882a593Smuzhiyun Say Y here to enable PCIe controller support on Qualcomm SoCs. The 205*4882a593Smuzhiyun PCIe controller uses the DesignWare core plus Qualcomm-specific 206*4882a593Smuzhiyun hardware wrappers. 207*4882a593Smuzhiyun 208*4882a593Smuzhiyunconfig PCIE_ARMADA_8K 209*4882a593Smuzhiyun bool "Marvell Armada-8K PCIe controller" 210*4882a593Smuzhiyun depends on ARCH_MVEBU || COMPILE_TEST 211*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 212*4882a593Smuzhiyun select PCIE_DW_HOST 213*4882a593Smuzhiyun help 214*4882a593Smuzhiyun Say Y here if you want to enable PCIe controller support on 215*4882a593Smuzhiyun Armada-8K SoCs. The PCIe controller on Armada-8K is based on 216*4882a593Smuzhiyun DesignWare hardware and therefore the driver re-uses the 217*4882a593Smuzhiyun DesignWare core functions to implement the driver. 218*4882a593Smuzhiyun 219*4882a593Smuzhiyunconfig PCIE_ARTPEC6 220*4882a593Smuzhiyun bool 221*4882a593Smuzhiyun 222*4882a593Smuzhiyunconfig PCIE_ARTPEC6_HOST 223*4882a593Smuzhiyun bool "Axis ARTPEC-6 PCIe controller Host Mode" 224*4882a593Smuzhiyun depends on MACH_ARTPEC6 || COMPILE_TEST 225*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 226*4882a593Smuzhiyun select PCIE_DW_HOST 227*4882a593Smuzhiyun select PCIE_ARTPEC6 228*4882a593Smuzhiyun help 229*4882a593Smuzhiyun Enables support for the PCIe controller in the ARTPEC-6 SoC to work in 230*4882a593Smuzhiyun host mode. This uses the DesignWare core. 231*4882a593Smuzhiyun 232*4882a593Smuzhiyunconfig PCIE_ARTPEC6_EP 233*4882a593Smuzhiyun bool "Axis ARTPEC-6 PCIe controller Endpoint Mode" 234*4882a593Smuzhiyun depends on MACH_ARTPEC6 || COMPILE_TEST 235*4882a593Smuzhiyun depends on PCI_ENDPOINT 236*4882a593Smuzhiyun select PCIE_DW_EP 237*4882a593Smuzhiyun select PCIE_ARTPEC6 238*4882a593Smuzhiyun help 239*4882a593Smuzhiyun Enables support for the PCIe controller in the ARTPEC-6 SoC to work in 240*4882a593Smuzhiyun endpoint mode. This uses the DesignWare core. 241*4882a593Smuzhiyun 242*4882a593Smuzhiyunconfig PCIE_INTEL_GW 243*4882a593Smuzhiyun bool "Intel Gateway PCIe host controller support" 244*4882a593Smuzhiyun depends on OF && (X86 || COMPILE_TEST) 245*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 246*4882a593Smuzhiyun select PCIE_DW_HOST 247*4882a593Smuzhiyun help 248*4882a593Smuzhiyun Say 'Y' here to enable PCIe Host controller support on Intel 249*4882a593Smuzhiyun Gateway SoCs. 250*4882a593Smuzhiyun The PCIe controller uses the DesignWare core plus Intel-specific 251*4882a593Smuzhiyun hardware wrappers. 252*4882a593Smuzhiyun 253*4882a593Smuzhiyunconfig PCIE_KIRIN 254*4882a593Smuzhiyun depends on OF && (ARM64 || COMPILE_TEST) 255*4882a593Smuzhiyun bool "HiSilicon Kirin series SoCs PCIe controllers" 256*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 257*4882a593Smuzhiyun select PCIE_DW_HOST 258*4882a593Smuzhiyun help 259*4882a593Smuzhiyun Say Y here if you want PCIe controller support 260*4882a593Smuzhiyun on HiSilicon Kirin series SoCs. 261*4882a593Smuzhiyun 262*4882a593Smuzhiyunconfig PCIE_HISI_STB 263*4882a593Smuzhiyun bool "HiSilicon STB SoCs PCIe controllers" 264*4882a593Smuzhiyun depends on ARCH_HISI || COMPILE_TEST 265*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 266*4882a593Smuzhiyun select PCIE_DW_HOST 267*4882a593Smuzhiyun help 268*4882a593Smuzhiyun Say Y here if you want PCIe controller support on HiSilicon STB SoCs 269*4882a593Smuzhiyun 270*4882a593Smuzhiyunconfig PCI_MESON 271*4882a593Smuzhiyun tristate "MESON PCIe controller" 272*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 273*4882a593Smuzhiyun default m if ARCH_MESON 274*4882a593Smuzhiyun select PCIE_DW_HOST 275*4882a593Smuzhiyun help 276*4882a593Smuzhiyun Say Y here if you want to enable PCI controller support on Amlogic 277*4882a593Smuzhiyun SoCs. The PCI controller on Amlogic is based on DesignWare hardware 278*4882a593Smuzhiyun and therefore the driver re-uses the DesignWare core functions to 279*4882a593Smuzhiyun implement the driver. 280*4882a593Smuzhiyun 281*4882a593Smuzhiyunconfig PCIE_TEGRA194 282*4882a593Smuzhiyun tristate 283*4882a593Smuzhiyun 284*4882a593Smuzhiyunconfig PCIE_TEGRA194_HOST 285*4882a593Smuzhiyun tristate "NVIDIA Tegra194 (and later) PCIe controller - Host Mode" 286*4882a593Smuzhiyun depends on ARCH_TEGRA_194_SOC || COMPILE_TEST 287*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 288*4882a593Smuzhiyun select PCIE_DW_HOST 289*4882a593Smuzhiyun select PHY_TEGRA194_P2U 290*4882a593Smuzhiyun select PCIE_TEGRA194 291*4882a593Smuzhiyun help 292*4882a593Smuzhiyun Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to 293*4882a593Smuzhiyun work in host mode. There are two instances of PCIe controllers in 294*4882a593Smuzhiyun Tegra194. This controller can work either as EP or RC. In order to 295*4882a593Smuzhiyun enable host-specific features PCIE_TEGRA194_HOST must be selected and 296*4882a593Smuzhiyun in order to enable device-specific features PCIE_TEGRA194_EP must be 297*4882a593Smuzhiyun selected. This uses the DesignWare core. 298*4882a593Smuzhiyun 299*4882a593Smuzhiyunconfig PCIE_TEGRA194_EP 300*4882a593Smuzhiyun tristate "NVIDIA Tegra194 (and later) PCIe controller - Endpoint Mode" 301*4882a593Smuzhiyun depends on ARCH_TEGRA_194_SOC || COMPILE_TEST 302*4882a593Smuzhiyun depends on PCI_ENDPOINT 303*4882a593Smuzhiyun select PCIE_DW_EP 304*4882a593Smuzhiyun select PHY_TEGRA194_P2U 305*4882a593Smuzhiyun select PCIE_TEGRA194 306*4882a593Smuzhiyun help 307*4882a593Smuzhiyun Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to 308*4882a593Smuzhiyun work in host mode. There are two instances of PCIe controllers in 309*4882a593Smuzhiyun Tegra194. This controller can work either as EP or RC. In order to 310*4882a593Smuzhiyun enable host-specific features PCIE_TEGRA194_HOST must be selected and 311*4882a593Smuzhiyun in order to enable device-specific features PCIE_TEGRA194_EP must be 312*4882a593Smuzhiyun selected. This uses the DesignWare core. 313*4882a593Smuzhiyun 314*4882a593Smuzhiyunconfig PCIE_UNIPHIER 315*4882a593Smuzhiyun bool "Socionext UniPhier PCIe host controllers" 316*4882a593Smuzhiyun depends on ARCH_UNIPHIER || COMPILE_TEST 317*4882a593Smuzhiyun depends on OF && HAS_IOMEM 318*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 319*4882a593Smuzhiyun select PCIE_DW_HOST 320*4882a593Smuzhiyun help 321*4882a593Smuzhiyun Say Y here if you want PCIe host controller support on UniPhier SoCs. 322*4882a593Smuzhiyun This driver supports LD20 and PXs3 SoCs. 323*4882a593Smuzhiyun 324*4882a593Smuzhiyunconfig PCIE_UNIPHIER_EP 325*4882a593Smuzhiyun bool "Socionext UniPhier PCIe endpoint controllers" 326*4882a593Smuzhiyun depends on ARCH_UNIPHIER || COMPILE_TEST 327*4882a593Smuzhiyun depends on OF && HAS_IOMEM 328*4882a593Smuzhiyun depends on PCI_ENDPOINT 329*4882a593Smuzhiyun select PCIE_DW_EP 330*4882a593Smuzhiyun help 331*4882a593Smuzhiyun Say Y here if you want PCIe endpoint controller support on 332*4882a593Smuzhiyun UniPhier SoCs. This driver supports Pro5 SoC. 333*4882a593Smuzhiyun 334*4882a593Smuzhiyunconfig PCIE_AL 335*4882a593Smuzhiyun bool "Amazon Annapurna Labs PCIe controller" 336*4882a593Smuzhiyun depends on OF && (ARM64 || COMPILE_TEST) 337*4882a593Smuzhiyun depends on PCI_MSI_IRQ_DOMAIN 338*4882a593Smuzhiyun select PCIE_DW_HOST 339*4882a593Smuzhiyun help 340*4882a593Smuzhiyun Say Y here to enable support of the Amazon's Annapurna Labs PCIe 341*4882a593Smuzhiyun controller IP on Amazon SoCs. The PCIe controller uses the DesignWare 342*4882a593Smuzhiyun core plus Annapurna Labs proprietary hardware wrappers. This is 343*4882a593Smuzhiyun required only for DT-based platforms. ACPI platforms with the 344*4882a593Smuzhiyun Annapurna Labs PCIe controller don't need to enable this. 345*4882a593Smuzhiyun 346*4882a593Smuzhiyunendmenu 347