| /OK3568_Linux_fs/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-dp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip DP PHY driver
6 * Author: Yakir Yang <ykk@@rock-chips.com>
13 #include <linux/phy/phy.h>
32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state() local
38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
48 clk_disable_unprepare(dp->phy_24m); in rockchip_set_phy_state()
[all …]
|
| H A D | phy-rockchip-naneng-edp.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
20 #include <linux/phy/phy.h>
92 { {0x3, 0x1, 0x0}, {0x5, 0x1, 0x7}, {0x6, 0x1, 0x6}, { -1, -1, -1} },
93 { {0x5, 0x1, 0x0}, {0x7, 0x1, 0x4}, { -1, -1, -1}, { -1, -1, -1} },
94 { {0x7, 0x1, 0x0}, { -1, -1, -1}, { -1, -1, -1}, { -1, -1, -1} },
98 struct phy_configure_opts_dp *dp, in rockchip_edp_phy_set_voltage() argument
103 amp = vp[dp->voltage[lane]][dp->pre[lane]].amp; in rockchip_edp_phy_set_voltage()
104 amp_scale = vp[dp->voltage[lane]][dp->pre[lane]].amp_scale; in rockchip_edp_phy_set_voltage()
105 emp = vp[dp->voltage[lane]][dp->pre[lane]].emp; in rockchip_edp_phy_set_voltage()
[all …]
|
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
7 tristate "Rockchip CSI2 D-PHY Driver"
16 tristate "Rockchip Display Port PHY Driver"
20 Enable this to support the Rockchip Display Port PHY.
32 will be called phy-rockchip-dphy-rx0.
35 tristate "Rockchip EMMC PHY Driver"
39 Enable this to support the Rockchip EMMC PHY.
50 tristate "Rockchip INNO HDMI PHY Driver"
55 Enable this to support the Rockchip Innosilicon HDMI PHY.
[all …]
|
| H A D | phy-rockchip-usbdp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
10 #include <linux/clk-provider.h>
22 #include <linux/phy/phy.h>
30 #include <linux/phy/phy-rockchip-usbdp.h>
57 /* u2phy-grf */
61 /* usb-grf */
65 /* usbdpphy-grf */
71 /* vo-grf */
95 struct phy_configure_opts_dp *dp);
[all …]
|
| H A D | phy-rockchip-samsung-hdptx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip HDMI/DP Combo PHY with Samsung IP block
14 #include <linux/phy/phy.h>
354 /* voltage swing 0, pre-emphasis 0->3 */
362 /* voltage swing 1, pre-emphasis 0->2 */
369 /* voltage swing 2, pre-emphasis 0->1 */
375 /* voltage swing 3, pre-emphasis 0 */
382 /* voltage swing 0, pre-emphasis 0->3 */
390 /* voltage swing 1, pre-emphasis 0->2 */
397 /* voltage swing 2, pre-emphasis 0->1 */
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/ |
| H A D | phy-rockchip-usbdp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USBDP Combo PHY with Samsung IP block
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3588-usbdp-phy
23 - description: phy ref clock.
24 - description: phy pcs immortal clock.
[all …]
|
| H A D | qcom,qmp-usb3-dp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP USB3 DP PHY controller
11 - Manu Gautam <mgautam@codeaurora.org>
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sc7180-qmp-usb3-phy
18 - qcom,sdm845-qmp-usb3-dp-phy
19 - qcom,sdm845-qmp-usb3-phy
[all …]
|
| H A D | phy-rockchip-typec.txt | 1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/xlnx/ |
| H A D | zynqmp_dp.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
31 #include <linux/phy/phy.h>
40 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
47 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
182 /* PHY configuration and status registers */
242 * struct zynqmp_dp_link_config - Common link config between source and sink
252 * struct zynqmp_dp_mode - Configured mode of DisplayPort
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/exynos/ |
| H A D | exynos_dp.txt | 5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
11 Base address of DP PHY register.
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_link.c | 1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/ |
| H A D | cdn-dp-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
11 #include <linux/phy/phy.h>
15 #include <sound/hdmi-codec.h>
24 #include "cdn-dp-core.h"
25 #include "cdn-dp-reg.h"
54 { .compatible = "rockchip,rk3399-cdn-dp",
61 static int cdn_dp_grf_write(struct cdn_dp_device *dp, in cdn_dp_grf_write() argument
66 ret = clk_prepare_enable(dp->grf_clk); in cdn_dp_grf_write()
68 DRM_DEV_ERROR(dp->dev, "Failed to prepare_enable grf clock\n"); in cdn_dp_grf_write()
[all …]
|
| H A D | dw-dp.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
8 * Zhang Yubing <yubing.zhang@rock-chips.com>
26 #include <linux/extcon-provider.h>
34 #include <linux/phy/phy.h>
39 #include <sound/hdmi-codec.h>
350 struct phy *phy; member
495 static int dw_dp_hdcp_init_keys(struct dw_dp *dp) in dw_dp_hdcp_init_keys() argument
503 regmap_read(dp->regmap, DPTX_HDCPREG_RMLSTS, &val); in dw_dp_hdcp_init_keys()
505 dev_info(dp->dev, "dpk keys already write\n"); in dw_dp_hdcp_init_keys()
[all …]
|
| /OK3568_Linux_fs/u-boot/drivers/phy/ |
| H A D | phy-rockchip-naneng-edp.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
10 #include <generic-phy.h>
86 { {0x3, 0x1, 0x0}, {0x5, 0x1, 0x7}, {0x6, 0x1, 0x6}, { -1, -1, -1} },
87 { {0x5, 0x1, 0x0}, {0x7, 0x1, 0x4}, { -1, -1, -1}, { -1, -1, -1} },
88 { {0x7, 0x1, 0x0}, { -1, -1, -1}, { -1, -1, -1}, { -1, -1, -1} },
92 struct phy_configure_opts_dp *dp, in rockchip_edp_phy_set_voltage() argument
97 amp = vp[dp->voltage[lane]][dp->pre[lane]].amp; in rockchip_edp_phy_set_voltage()
98 amp_scale = vp[dp->voltage[lane]][dp->pre[lane]].amp_scale; in rockchip_edp_phy_set_voltage()
99 emp = vp[dp->voltage[lane]][dp->pre[lane]].emp; in rockchip_edp_phy_set_voltage()
[all …]
|
| H A D | phy-rockchip-usbdp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
14 #include <generic-phy.h>
24 #include <linux/usb/phy-rockchip-usbdp.h>
51 * struct reg_sequence - An individual write from a sequence of writes.
67 /* u2phy-grf */
71 /* usb-grf */
75 /* usbdpphy-grf */
98 struct phy_configure_opts_dp *dp);
100 struct phy_configure_opts_dp *dp);
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/phy/samsung/ |
| H A D | phy-exynos-dp-video.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos SoC series Display Port PHY driver
17 #include <linux/phy/phy.h>
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
31 static int exynos_dp_video_phy_power_on(struct phy *phy) in exynos_dp_video_phy_power_on() argument
33 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_on()
35 /* Disable power isolation on DP-PHY */ in exynos_dp_video_phy_power_on()
36 return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset, in exynos_dp_video_phy_power_on()
40 static int exynos_dp_video_phy_power_off(struct phy *phy) in exynos_dp_video_phy_power_off() argument
42 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_off()
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/bridge/ |
| H A D | analogix_dp.txt | 3 Required properties for dp-controller:
4 -compatible:
6 * "samsung,exynos5-dp"
7 * "rockchip,rk3288-dp"
8 * "rockchip,rk3399-edp"
9 -reg:
12 -interrupts:
14 -clocks:
15 from common clock binding: handle to dp clock.
16 -clock-names:
[all …]
|
| H A D | cdns,mhdp8546.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
23 - description:
24 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
26 included in the associated PHY.
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/ |
| H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 ccflags-y := -I $(srctree)/$(src)
3 ccflags-y += -I $(srctree)/$(src)/disp/dpu1
4 ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
5 ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
7 msm-y := \
99 msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
100 dp/dp_debug.o
102 msm-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o
104 msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
[all …]
|
| /OK3568_Linux_fs/u-boot/drivers/video/drm/ |
| H A D | Kconfig | 5 select PHY
7 Rockchip SoCs provide video output capabilities for High-Definition
8 Multimedia Interface (HDMI), Low-voltage Differential Signalling
11 This driver supports the on-chip video output device, and targets the
37 Driver for Maxim MAX96755F GMSL2 Serializer with MIPI-DSI Input.
40 bool "Rohm BU18RL82-based panels"
47 bool "Maxim MAX96752F-based panels"
89 bool "Rockchip specific extensions for INNO HDMI PHY"
92 This selects support for INNO HDMI PHY. If you want to
97 tristate "Rockchip INNO MIPI PHY driver"
[all …]
|
| H A D | dw-dp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
18 #include <generic-phy.h>
21 #include <linux/media-bus-format.h>
24 #include <generic-phy.h>
223 struct phy phy; member
324 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size) in dw_dp_aux_write_data() argument
329 size_t num = min_t(size_t, size - i * 4, 4); in dw_dp_aux_write_data()
335 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value); in dw_dp_aux_write_data()
341 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size) in dw_dp_aux_read_data() argument
[all …]
|
| /OK3568_Linux_fs/kernel/net/dsa/ |
| H A D | port.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2017 Savoir-faire Linux Inc.
22 struct raw_notifier_head *nh = &dst->nh; in dsa_broadcast()
33 static int dsa_port_notify(const struct dsa_port *dp, unsigned long e, void *v) in dsa_port_notify() argument
35 struct raw_notifier_head *nh = &dp->ds->dst->nh; in dsa_port_notify()
43 int dsa_port_set_state(struct dsa_port *dp, u8 state, in dsa_port_set_state() argument
46 struct dsa_switch *ds = dp->ds; in dsa_port_set_state()
47 int port = dp->index; in dsa_port_set_state()
50 return ds->ops->port_stp_state_set ? 0 : -EOPNOTSUPP; in dsa_port_set_state()
52 if (ds->ops->port_stp_state_set) in dsa_port_set_state()
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dp/ |
| H A D | dp_parser.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
10 #include <linux/phy/phy.h>
11 #include <linux/phy/phy-dp.h>
16 #define DP_LABEL "MDSS DP DISPLAY"
45 * struct dp_display_data - display related device tree data.
48 * @phy_node: reference to phy device
62 * struct dp_ctrl_resource - controller's IO related data
65 * @phy_io: phy's mapped memory address
69 struct phy *phy; member
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_link_encoder.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
54 SRI(DP_CONFIG, DP, id), \
55 SRI(DP_DPHY_CNTL, DP, id), \
56 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
57 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
58 SRI(DP_DPHY_SYM0, DP, id), \
59 SRI(DP_DPHY_SYM1, DP, id), \
60 SRI(DP_DPHY_SYM2, DP, id), \
61 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
62 SRI(DP_LINK_CNTL, DP, id), \
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/analogix/ |
| H A D | analogix_dp_core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Analogix DP (Display Port) core interface driver.
11 #include <linux/extcon-provider.h>
20 #include <linux/phy/phy.h>
59 static bool analogix_dp_bandwidth_ok(struct analogix_dp_device *dp, in analogix_dp_bandwidth_ok() argument
66 if (dp->plat_data->skip_connector) in analogix_dp_bandwidth_ok()
69 info = &dp->connector.display_info; in analogix_dp_bandwidth_ok()
70 if (info->bpc) in analogix_dp_bandwidth_ok()
71 bpp = 3 * info->bpc; in analogix_dp_bandwidth_ok()
73 req_bw = mode->clock * bpp / 8; in analogix_dp_bandwidth_ok()
[all …]
|