1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/gpio.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_platform.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/reset.h>
26 #include <linux/usb/ch9.h>
27 #include <linux/usb/typec_dp.h>
28 #include <linux/usb/typec_mux.h>
29
30 #include <linux/phy/phy-rockchip-usbdp.h>
31
32 #define BIT_WRITEABLE_SHIFT 16
33
34 enum {
35 DP_BW_RBR,
36 DP_BW_HBR,
37 DP_BW_HBR2,
38 DP_BW_HBR3,
39 };
40
41 enum {
42 UDPHY_MODE_NONE = 0,
43 UDPHY_MODE_USB = BIT(0),
44 UDPHY_MODE_DP = BIT(1),
45 UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
46 };
47
48 struct udphy_grf_reg {
49 unsigned int offset;
50 unsigned int bitend;
51 unsigned int bitstart;
52 unsigned int disable;
53 unsigned int enable;
54 };
55
56 struct udphy_grf_cfg {
57 /* u2phy-grf */
58 struct udphy_grf_reg bvalid_phy_con;
59 struct udphy_grf_reg bvalid_grf_con;
60
61 /* usb-grf */
62 struct udphy_grf_reg usb3otg0_cfg;
63 struct udphy_grf_reg usb3otg1_cfg;
64
65 /* usbdpphy-grf */
66 struct udphy_grf_reg low_pwrn;
67 struct udphy_grf_reg rx_lfps;
68 };
69
70 struct udphy_vogrf_cfg {
71 /* vo-grf */
72 struct udphy_grf_reg hpd_trigger;
73 };
74
75 struct dp_tx_drv_ctrl {
76 u32 trsv_reg0204;
77 u32 trsv_reg0205;
78 u32 trsv_reg0206;
79 u32 trsv_reg0207;
80 };
81
82 struct rockchip_udphy;
83
84 struct rockchip_udphy_cfg {
85 /* resets to be requested */
86 const char * const *rst_list;
87 int num_rsts;
88
89 struct udphy_grf_cfg grfcfg;
90 struct udphy_vogrf_cfg vogrfcfg[2];
91 const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4];
92 const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4];
93 int (*combophy_init)(struct rockchip_udphy *udphy);
94 int (*dp_phy_set_rate)(struct rockchip_udphy *udphy,
95 struct phy_configure_opts_dp *dp);
96 int (*dp_phy_set_voltages)(struct rockchip_udphy *udphy,
97 struct phy_configure_opts_dp *dp);
98 int (*hpd_event_trigger)(struct rockchip_udphy *udphy, bool hpd);
99 int (*dplane_enable)(struct rockchip_udphy *udphy, int dp_lanes);
100 int (*dplane_select)(struct rockchip_udphy *udphy);
101 };
102
103 struct rockchip_udphy {
104 struct device *dev;
105 struct regmap *pma_regmap;
106 struct regmap *u2phygrf;
107 struct regmap *udphygrf;
108 struct regmap *usbgrf;
109 struct regmap *vogrf;
110 struct typec_switch *sw;
111 struct typec_mux *mux;
112 struct mutex mutex; /* mutex to protect access to individual PHYs */
113
114 /* clocks and rests */
115 int num_clks;
116 struct clk_bulk_data *clks;
117 struct clk *refclk;
118 struct reset_control **rsts;
119
120 /* PHY status management */
121 bool flip;
122 bool mode_change;
123 u8 mode;
124 u8 status;
125
126 /* utilized for USB */
127 bool hs; /* flag for high-speed */
128
129 /* utilized for DP */
130 struct gpio_desc *sbu1_dc_gpio;
131 struct gpio_desc *sbu2_dc_gpio;
132 u32 lane_mux_sel[4];
133 u32 dp_lane_sel[4];
134 u32 dp_aux_dout_sel;
135 u32 dp_aux_din_sel;
136 bool dp_sink_hpd_sel;
137 bool dp_sink_hpd_cfg;
138 u8 bw;
139 int id;
140
141 /* PHY const config */
142 const struct rockchip_udphy_cfg *cfgs;
143 };
144
145 static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = {
146 /* voltage swing 0, pre-emphasis 0->3 */
147 {
148 { 0x20, 0x10, 0x42, 0xe5 },
149 { 0x26, 0x14, 0x42, 0xe5 },
150 { 0x29, 0x18, 0x42, 0xe5 },
151 { 0x2b, 0x1c, 0x43, 0xe7 },
152 },
153
154 /* voltage swing 1, pre-emphasis 0->2 */
155 {
156 { 0x23, 0x10, 0x42, 0xe7 },
157 { 0x2a, 0x17, 0x43, 0xe7 },
158 { 0x2b, 0x1a, 0x43, 0xe7 },
159 },
160
161 /* voltage swing 2, pre-emphasis 0->1 */
162 {
163 { 0x27, 0x10, 0x42, 0xe7 },
164 { 0x2b, 0x17, 0x43, 0xe7 },
165 },
166
167 /* voltage swing 3, pre-emphasis 0 */
168 {
169 { 0x29, 0x10, 0x43, 0xe7 },
170 },
171 };
172
173 static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_typec[4][4] = {
174 /* voltage swing 0, pre-emphasis 0->3 */
175 {
176 { 0x20, 0x10, 0x42, 0xe5 },
177 { 0x26, 0x14, 0x42, 0xe5 },
178 { 0x29, 0x18, 0x42, 0xe5 },
179 { 0x2b, 0x1c, 0x43, 0xe7 },
180 },
181
182 /* voltage swing 1, pre-emphasis 0->2 */
183 {
184 { 0x23, 0x10, 0x42, 0xe7 },
185 { 0x2a, 0x17, 0x43, 0xe7 },
186 { 0x2b, 0x1a, 0x43, 0xe7 },
187 },
188
189 /* voltage swing 2, pre-emphasis 0->1 */
190 {
191 { 0x27, 0x10, 0x43, 0x67 },
192 { 0x2b, 0x17, 0x43, 0xe7 },
193 },
194
195 /* voltage swing 3, pre-emphasis 0 */
196 {
197 { 0x29, 0x10, 0x43, 0xe7 },
198 },
199 };
200
201 static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = {
202 /* voltage swing 0, pre-emphasis 0->3 */
203 {
204 { 0x21, 0x10, 0x42, 0xe5 },
205 { 0x26, 0x14, 0x42, 0xe5 },
206 { 0x26, 0x16, 0x43, 0xe5 },
207 { 0x2a, 0x19, 0x43, 0xe7 },
208 },
209
210 /* voltage swing 1, pre-emphasis 0->2 */
211 {
212 { 0x24, 0x10, 0x42, 0xe7 },
213 { 0x2a, 0x17, 0x43, 0xe7 },
214 { 0x2b, 0x1a, 0x43, 0xe7 },
215 },
216
217 /* voltage swing 2, pre-emphasis 0->1 */
218 {
219 { 0x28, 0x10, 0x42, 0xe7 },
220 { 0x2b, 0x17, 0x43, 0xe7 },
221 },
222
223 /* voltage swing 3, pre-emphasis 0 */
224 {
225 { 0x28, 0x10, 0x43, 0xe7 },
226 },
227 };
228
229 static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = {
230 /* voltage swing 0, pre-emphasis 0->3 */
231 {
232 { 0x21, 0x10, 0x42, 0xe5 },
233 { 0x26, 0x14, 0x42, 0xe5 },
234 { 0x26, 0x16, 0x43, 0xe5 },
235 { 0x29, 0x18, 0x43, 0xe7 },
236 },
237
238 /* voltage swing 1, pre-emphasis 0->2 */
239 {
240 { 0x24, 0x10, 0x42, 0xe7 },
241 { 0x2a, 0x18, 0x43, 0xe7 },
242 { 0x2b, 0x1b, 0x43, 0xe7 }
243 },
244
245 /* voltage swing 2, pre-emphasis 0->1 */
246 {
247 { 0x27, 0x10, 0x42, 0xe7 },
248 { 0x2b, 0x18, 0x43, 0xe7 }
249 },
250
251 /* voltage swing 3, pre-emphasis 0 */
252 {
253 { 0x28, 0x10, 0x43, 0xe7 },
254 },
255 };
256
257 static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = {
258 {0x0090, 0x68}, {0x0094, 0x68},
259 {0x0128, 0x24}, {0x012c, 0x44},
260 {0x0130, 0x3f}, {0x0134, 0x44},
261 {0x015c, 0xa9}, {0x0160, 0x71},
262 {0x0164, 0x71}, {0x0168, 0xa9},
263 {0x0174, 0xa9}, {0x0178, 0x71},
264 {0x017c, 0x71}, {0x0180, 0xa9},
265 {0x018c, 0x41}, {0x0190, 0x00},
266 {0x0194, 0x05}, {0x01ac, 0x2a},
267 {0x01b0, 0x17}, {0x01b4, 0x17},
268 {0x01b8, 0x2a}, {0x01c8, 0x04},
269 {0x01cc, 0x08}, {0x01d0, 0x08},
270 {0x01d4, 0x04}, {0x01d8, 0x20},
271 {0x01dc, 0x01}, {0x01e0, 0x09},
272 {0x01e4, 0x03}, {0x01f0, 0x29},
273 {0x01f4, 0x02}, {0x01f8, 0x02},
274 {0x01fc, 0x29}, {0x0208, 0x2a},
275 {0x020c, 0x17}, {0x0210, 0x17},
276 {0x0214, 0x2a}, {0x0224, 0x20},
277 {0x03f0, 0x0a}, {0x03f4, 0x07},
278 {0x03f8, 0x07}, {0x03fc, 0x0c},
279 {0x0404, 0x12}, {0x0408, 0x1a},
280 {0x040c, 0x1a}, {0x0410, 0x3f},
281 {0x0ce0, 0x68}, {0x0ce8, 0xd0},
282 {0x0cf0, 0x87}, {0x0cf8, 0x70},
283 {0x0d00, 0x70}, {0x0d08, 0xa9},
284 {0x1ce0, 0x68}, {0x1ce8, 0xd0},
285 {0x1cf0, 0x87}, {0x1cf8, 0x70},
286 {0x1d00, 0x70}, {0x1d08, 0xa9},
287 {0x0a3c, 0xd0}, {0x0a44, 0xd0},
288 {0x0a48, 0x01}, {0x0a4c, 0x0d},
289 {0x0a54, 0xe0}, {0x0a5c, 0xe0},
290 {0x0a64, 0xa8}, {0x1a3c, 0xd0},
291 {0x1a44, 0xd0}, {0x1a48, 0x01},
292 {0x1a4c, 0x0d}, {0x1a54, 0xe0},
293 {0x1a5c, 0xe0}, {0x1a64, 0xa8}
294 };
295
296 static const struct reg_sequence rk3588_udphy_26m_refclk_cfg[] = {
297 {0x0830, 0x07}, {0x085c, 0x80},
298 {0x1030, 0x07}, {0x105c, 0x80},
299 {0x1830, 0x07}, {0x185c, 0x80},
300 {0x2030, 0x07}, {0x205c, 0x80},
301 {0x0228, 0x38}, {0x0104, 0x44},
302 {0x0248, 0x44}, {0x038C, 0x02},
303 {0x0878, 0x04}, {0x1878, 0x04},
304 {0x0898, 0x77}, {0x1898, 0x77},
305 {0x0054, 0x01}, {0x00e0, 0x38},
306 {0x0060, 0x24}, {0x0064, 0x77},
307 {0x0070, 0x76}, {0x0234, 0xE8},
308 {0x0AF4, 0x15}, {0x1AF4, 0x15},
309 {0x081C, 0xE5}, {0x181C, 0xE5},
310 {0x099C, 0x48}, {0x199C, 0x48},
311 {0x09A4, 0x07}, {0x09A8, 0x22},
312 {0x19A4, 0x07}, {0x19A8, 0x22},
313 {0x09B8, 0x3E}, {0x19B8, 0x3E},
314 {0x09E4, 0x02}, {0x19E4, 0x02},
315 {0x0A34, 0x1E}, {0x1A34, 0x1E},
316 {0x0A98, 0x2F}, {0x1A98, 0x2F},
317 {0x0c30, 0x0E}, {0x0C48, 0x06},
318 {0x1C30, 0x0E}, {0x1C48, 0x06},
319 {0x028C, 0x18}, {0x0AF0, 0x00},
320 {0x1AF0, 0x00}
321 };
322
323 static const struct reg_sequence rk3588_udphy_init_sequence[] = {
324 {0x0104, 0x44}, {0x0234, 0xE8},
325 {0x0248, 0x44}, {0x028C, 0x18},
326 {0x081C, 0xE5}, {0x0878, 0x00},
327 {0x0994, 0x1C}, {0x0AF0, 0x00},
328 {0x181C, 0xE5}, {0x1878, 0x00},
329 {0x1994, 0x1C}, {0x1AF0, 0x00},
330 {0x0428, 0x60}, {0x0D58, 0x33},
331 {0x1D58, 0x33}, {0x0990, 0x74},
332 {0x0D64, 0x17}, {0x08C8, 0x13},
333 {0x1990, 0x74}, {0x1D64, 0x17},
334 {0x18C8, 0x13}, {0x0D90, 0x40},
335 {0x0DA8, 0x40}, {0x0DC0, 0x40},
336 {0x0DD8, 0x40}, {0x1D90, 0x40},
337 {0x1DA8, 0x40}, {0x1DC0, 0x40},
338 {0x1DD8, 0x40}, {0x03C0, 0x30},
339 {0x03C4, 0x06}, {0x0E10, 0x00},
340 {0x1E10, 0x00}, {0x043C, 0x0F},
341 {0x0D2C, 0xFF}, {0x1D2C, 0xFF},
342 {0x0D34, 0x0F}, {0x1D34, 0x0F},
343 {0x08FC, 0x2A}, {0x0914, 0x28},
344 {0x0A30, 0x03}, {0x0E38, 0x05},
345 {0x0ECC, 0x27}, {0x0ED0, 0x22},
346 {0x0ED4, 0x26}, {0x18FC, 0x2A},
347 {0x1914, 0x28}, {0x1A30, 0x03},
348 {0x1E38, 0x05}, {0x1ECC, 0x27},
349 {0x1ED0, 0x22}, {0x1ED4, 0x26},
350 {0x0048, 0x0F}, {0x0060, 0x3C},
351 {0x0064, 0xF7}, {0x006C, 0x20},
352 {0x0070, 0x7D}, {0x0074, 0x68},
353 {0x0AF4, 0x1A}, {0x1AF4, 0x1A},
354 {0x0440, 0x3F}, {0x10D4, 0x08},
355 {0x20D4, 0x08}, {0x00D4, 0x30},
356 {0x0024, 0x6e},
357 };
358
grfreg_write(struct regmap * base,const struct udphy_grf_reg * reg,bool en)359 static inline int grfreg_write(struct regmap *base,
360 const struct udphy_grf_reg *reg, bool en)
361 {
362 u32 val, mask, tmp;
363
364 tmp = en ? reg->enable : reg->disable;
365 mask = GENMASK(reg->bitend, reg->bitstart);
366 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
367
368 return regmap_write(base, reg->offset, val);
369 }
370
udphy_clk_init(struct rockchip_udphy * udphy,struct device * dev)371 static int udphy_clk_init(struct rockchip_udphy *udphy, struct device *dev)
372 {
373 int i;
374
375 udphy->num_clks = devm_clk_bulk_get_all(dev, &udphy->clks);
376 if (udphy->num_clks < 1)
377 return -ENODEV;
378
379 /* used for configure phy reference clock frequency */
380 for (i = 0; i < udphy->num_clks; i++) {
381 if (!strncmp(udphy->clks[i].id, "refclk", 6)) {
382 udphy->refclk = udphy->clks[i].clk;
383 break;
384 }
385 }
386
387 if (!udphy->refclk)
388 dev_warn(udphy->dev, "no refclk found\n");
389
390 return 0;
391 }
392
udphy_reset_init(struct rockchip_udphy * udphy,struct device * dev)393 static int udphy_reset_init(struct rockchip_udphy *udphy, struct device *dev)
394 {
395 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
396 int idx;
397
398 udphy->rsts = devm_kcalloc(dev, cfg->num_rsts,
399 sizeof(*udphy->rsts), GFP_KERNEL);
400 if (!udphy->rsts)
401 return -ENOMEM;
402
403 for (idx = 0; idx < cfg->num_rsts; idx++) {
404 struct reset_control *rst;
405 const char *name = cfg->rst_list[idx];
406
407 rst = devm_reset_control_get(dev, name);
408 if (IS_ERR(rst)) {
409 dev_err(dev, "failed to get %s reset\n", name);
410 devm_kfree(dev, (void *)udphy->rsts);
411 return PTR_ERR(rst);
412 }
413
414 udphy->rsts[idx] = rst;
415 }
416
417 return 0;
418 }
419
udphy_get_rst_idx(const char * const * list,int num,char * name)420 static int udphy_get_rst_idx(const char * const *list, int num, char *name)
421 {
422 int idx;
423
424 for (idx = 0; idx < num; idx++) {
425 if (!strcmp(list[idx], name))
426 return idx;
427 }
428
429 return -EINVAL;
430 }
431
udphy_reset_assert(struct rockchip_udphy * udphy,char * name)432 static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name)
433 {
434 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
435 int idx;
436
437 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
438 if (idx < 0)
439 return idx;
440
441 return reset_control_assert(udphy->rsts[idx]);
442 }
443
udphy_reset_deassert(struct rockchip_udphy * udphy,char * name)444 static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name)
445 {
446 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
447 int idx;
448
449 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
450 if (idx < 0)
451 return idx;
452
453 return reset_control_deassert(udphy->rsts[idx]);
454 }
455
udphy_u3_port_disable(struct rockchip_udphy * udphy,u8 disable)456 static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable)
457 {
458 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
459 const struct udphy_grf_reg *preg;
460
461 preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
462 grfreg_write(udphy->usbgrf, preg, disable);
463 }
464
udphy_usb_bvalid_enable(struct rockchip_udphy * udphy,u8 enable)465 static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable)
466 {
467 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
468
469 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
470 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
471 }
472
473 /*
474 * In usb/dp combo phy driver, here are 2 ways to mapping lanes.
475 *
476 * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
477 * ---------------------------------------------------------------------------
478 * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3
479 * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
480 * C/E(Normal) dpln3 dpln2 dpln0 dpln1
481 * C/E(Flip ) dpln0 dpln1 dpln3 dpln2
482 * D/F(Normal) usbrx usbtx dpln0 dpln1
483 * D/F(Flip ) dpln0 dpln1 usbrx usbtx
484 * A(Normal ) dpln3 dpln1 dpln2 dpln0
485 * A(Flip ) dpln2 dpln0 dpln3 dpln1
486 * B(Normal ) usbrx usbtx dpln1 dpln0
487 * B(Flip ) dpln1 dpln0 usbrx usbtx
488 * ---------------------------------------------------------------------------
489 *
490 * 2 Mapping the lanes in dtsi
491 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
492 * sample as follow:
493 * ---------------------------------------------------------------------------
494 * B11-B10 A2-A3 A11-A10 B2-B3
495 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
496 * <0 1 2 3> dpln0 dpln1 dpln2 dpln3
497 * <2 3 0 1> dpln2 dpln3 dpln0 dpln1
498 * ---------------------------------------------------------------------------
499 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
500 * sample as follow:
501 * ---------------------------------------------------------------------------
502 * B11-B10 A2-A3 A11-A10 B2-B3
503 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
504 * <0 1> dpln0 dpln1 usbrx usbtx
505 * <2 3> usbrx usbtx dpln0 dpln1
506 * ---------------------------------------------------------------------------
507 */
508
udphy_dplane_select(struct rockchip_udphy * udphy)509 static int udphy_dplane_select(struct rockchip_udphy *udphy)
510 {
511 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
512
513 if (cfg->dplane_select)
514 return cfg->dplane_select(udphy);
515
516 return 0;
517 }
518
udphy_dplane_get(struct rockchip_udphy * udphy)519 static int udphy_dplane_get(struct rockchip_udphy *udphy)
520 {
521 int dp_lanes;
522
523 switch (udphy->mode) {
524 case UDPHY_MODE_DP:
525 dp_lanes = 4;
526 break;
527 case UDPHY_MODE_DP_USB:
528 dp_lanes = 2;
529 break;
530 case UDPHY_MODE_USB:
531 fallthrough;
532 default:
533 dp_lanes = 0;
534 break;
535 }
536
537 return dp_lanes;
538 }
539
udphy_dplane_enable(struct rockchip_udphy * udphy,int dp_lanes)540 static int udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes)
541 {
542 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
543 int ret = 0;
544
545 if (cfg->dplane_enable)
546 ret = cfg->dplane_enable(udphy, dp_lanes);
547
548 return ret;
549 }
550
upphy_set_typec_default_mapping(struct rockchip_udphy * udphy)551 static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy)
552 {
553 if (udphy->flip) {
554 udphy->dp_lane_sel[0] = 0;
555 udphy->dp_lane_sel[1] = 1;
556 udphy->dp_lane_sel[2] = 3;
557 udphy->dp_lane_sel[3] = 2;
558 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
559 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
560 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
561 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
562 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
563 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
564 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1);
565 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
566 } else {
567 udphy->dp_lane_sel[0] = 2;
568 udphy->dp_lane_sel[1] = 3;
569 udphy->dp_lane_sel[2] = 1;
570 udphy->dp_lane_sel[3] = 0;
571 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
572 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
573 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
574 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
575 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
576 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
577 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
578 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1);
579 }
580
581 udphy->mode = UDPHY_MODE_DP_USB;
582
583 return 0;
584 }
585
udphy_orien_sw_set(struct typec_switch * sw,enum typec_orientation orien)586 static int udphy_orien_sw_set(struct typec_switch *sw,
587 enum typec_orientation orien)
588 {
589 struct rockchip_udphy *udphy = typec_switch_get_drvdata(sw);
590
591 mutex_lock(&udphy->mutex);
592
593 if (orien == TYPEC_ORIENTATION_NONE) {
594 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
595 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
596 /* unattached */
597 udphy_usb_bvalid_enable(udphy, false);
598 goto unlock_ret;
599 }
600
601 udphy->flip = (orien == TYPEC_ORIENTATION_REVERSE) ? true : false;
602 upphy_set_typec_default_mapping(udphy);
603 udphy_usb_bvalid_enable(udphy, true);
604
605 unlock_ret:
606 mutex_unlock(&udphy->mutex);
607 return 0;
608 }
609
udphy_setup_orien_switch(struct rockchip_udphy * udphy)610 static int udphy_setup_orien_switch(struct rockchip_udphy *udphy)
611 {
612 struct typec_switch_desc sw_desc = { };
613
614 sw_desc.drvdata = udphy;
615 sw_desc.fwnode = dev_fwnode(udphy->dev);
616 sw_desc.set = udphy_orien_sw_set;
617
618 udphy->sw = typec_switch_register(udphy->dev, &sw_desc);
619 if (IS_ERR(udphy->sw)) {
620 dev_err(udphy->dev, "Error register typec orientation switch: %ld\n",
621 PTR_ERR(udphy->sw));
622 return PTR_ERR(udphy->sw);
623 }
624
625 return 0;
626 }
627
udphy_orien_switch_unregister(void * data)628 static void udphy_orien_switch_unregister(void *data)
629 {
630 struct rockchip_udphy *udphy = data;
631
632 typec_switch_unregister(udphy->sw);
633 }
634
udphy_setup(struct rockchip_udphy * udphy)635 static int udphy_setup(struct rockchip_udphy *udphy)
636 {
637 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
638 int ret = 0;
639
640 ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
641 if (ret) {
642 dev_err(udphy->dev, "failed to enable clk\n");
643 return ret;
644 }
645
646 if (cfg->combophy_init) {
647 ret = cfg->combophy_init(udphy);
648 if (ret) {
649 dev_err(udphy->dev, "failed to init combophy\n");
650 clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
651 return ret;
652 }
653 }
654
655 return 0;
656 }
657
udphy_disable(struct rockchip_udphy * udphy)658 static int udphy_disable(struct rockchip_udphy *udphy)
659 {
660 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
661 int i;
662
663 clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
664
665 for (i = 0; i < cfg->num_rsts; i++)
666 reset_control_assert(udphy->rsts[i]);
667
668 return 0;
669 }
670
udphy_parse_lane_mux_data(struct rockchip_udphy * udphy,struct device * dev)671 static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device *dev)
672 {
673 struct device_node *np = dev->of_node;
674 struct property *prop;
675 int ret, i, len, num_lanes;
676
677 prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
678 if (!prop) {
679 dev_dbg(dev, "failed to find dp lane mux, following dp alt mode\n");
680 udphy->mode = UDPHY_MODE_USB;
681 return 0;
682 }
683
684 num_lanes = len / sizeof(u32);
685
686 if (num_lanes != 2 && num_lanes != 4) {
687 dev_err(dev, "invalid number of lane mux\n");
688 return -EINVAL;
689 }
690
691 ret = of_property_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes);
692 if (ret) {
693 dev_err(dev, "get dp lane mux failed\n");
694 return -EINVAL;
695 }
696
697 for (i = 0; i < num_lanes; i++) {
698 int j;
699
700 if (udphy->dp_lane_sel[i] > 3) {
701 dev_err(dev, "lane mux between 0 and 3, exceeding the range\n");
702 return -EINVAL;
703 }
704
705 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;
706
707 for (j = i + 1; j < num_lanes; j++) {
708 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
709 dev_err(dev, "set repeat lane mux value\n");
710 return -EINVAL;
711 }
712 }
713 }
714
715 udphy->mode = UDPHY_MODE_DP;
716 if (num_lanes == 2) {
717 udphy->mode |= UDPHY_MODE_USB;
718 udphy->flip = udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP ? true : false;
719 }
720
721 return 0;
722 }
723
udphy_get_initial_status(struct rockchip_udphy * udphy)724 static int udphy_get_initial_status(struct rockchip_udphy *udphy)
725 {
726 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
727 int ret, i;
728 u32 value;
729
730 ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
731 if (ret) {
732 dev_err(udphy->dev, "failed to enable clk\n");
733 return ret;
734 }
735
736 for (i = 0; i < cfg->num_rsts; i++)
737 reset_control_deassert(udphy->rsts[i]);
738
739 regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value);
740 if (FIELD_GET(CMN_DP_LANE_MUX_ALL, value) && FIELD_GET(CMN_DP_LANE_EN_ALL, value))
741 udphy->status = UDPHY_MODE_DP;
742 else
743 udphy_disable(udphy);
744
745 return 0;
746 }
747
udphy_parse_dt(struct rockchip_udphy * udphy,struct device * dev)748 static int udphy_parse_dt(struct rockchip_udphy *udphy, struct device *dev)
749 {
750 struct device_node *np = dev->of_node;
751 enum usb_device_speed maximum_speed;
752 int ret;
753
754 udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf");
755 if (IS_ERR(udphy->u2phygrf)) {
756 if (PTR_ERR(udphy->u2phygrf) == -ENODEV) {
757 dev_warn(dev, "missing u2phy-grf dt node\n");
758 udphy->u2phygrf = NULL;
759 } else {
760 return PTR_ERR(udphy->u2phygrf);
761 }
762 }
763
764 udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf");
765 if (IS_ERR(udphy->udphygrf)) {
766 if (PTR_ERR(udphy->udphygrf) == -ENODEV) {
767 dev_warn(dev, "missing usbdpphy-grf dt node\n");
768 udphy->udphygrf = NULL;
769 } else {
770 return PTR_ERR(udphy->udphygrf);
771 }
772 }
773
774 udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf");
775 if (IS_ERR(udphy->usbgrf)) {
776 if (PTR_ERR(udphy->usbgrf) == -ENODEV) {
777 dev_warn(dev, "missing usb-grf dt node\n");
778 udphy->usbgrf = NULL;
779 } else {
780 return PTR_ERR(udphy->usbgrf);
781 }
782 }
783
784 udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf");
785 if (IS_ERR(udphy->vogrf)) {
786 if (PTR_ERR(udphy->vogrf) == -ENODEV) {
787 dev_warn(dev, "missing vo-grf dt node\n");
788 udphy->vogrf = NULL;
789 } else {
790 return PTR_ERR(udphy->vogrf);
791 }
792 }
793
794 ret = udphy_parse_lane_mux_data(udphy, dev);
795 if (ret)
796 return ret;
797
798 udphy->sbu1_dc_gpio = devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT_LOW);
799 if (IS_ERR(udphy->sbu1_dc_gpio))
800 return PTR_ERR(udphy->sbu1_dc_gpio);
801
802 udphy->sbu2_dc_gpio = devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT_LOW);
803 if (IS_ERR(udphy->sbu2_dc_gpio))
804 return PTR_ERR(udphy->sbu2_dc_gpio);
805
806 if (device_property_present(dev, "maximum-speed")) {
807 maximum_speed = usb_get_maximum_speed(dev);
808 udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;
809 }
810
811 ret = udphy_clk_init(udphy, dev);
812 if (ret)
813 return ret;
814
815 ret = udphy_reset_init(udphy, dev);
816 if (ret)
817 return ret;
818
819 return 0;
820 }
821
udphy_power_on(struct rockchip_udphy * udphy,u8 mode)822 static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
823 {
824 int ret;
825
826 if (!(udphy->mode & mode)) {
827 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
828 return 0;
829 }
830
831 if (udphy->status == UDPHY_MODE_NONE) {
832 udphy->mode_change = false;
833 ret = udphy_setup(udphy);
834 if (ret)
835 return ret;
836
837 if (udphy->mode & UDPHY_MODE_USB)
838 udphy_u3_port_disable(udphy, false);
839 } else if (udphy->mode_change) {
840 udphy->mode_change = false;
841 udphy->status = UDPHY_MODE_NONE;
842 if (udphy->mode == UDPHY_MODE_DP)
843 udphy_u3_port_disable(udphy, true);
844
845 ret = udphy_disable(udphy);
846 if (ret)
847 return ret;
848 ret = udphy_setup(udphy);
849 if (ret)
850 return ret;
851 }
852
853 udphy->status |= mode;
854
855 return 0;
856 }
857
udphy_power_off(struct rockchip_udphy * udphy,u8 mode)858 static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
859 {
860 int ret;
861
862 if (!(udphy->mode & mode)) {
863 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
864 return 0;
865 }
866
867 if (!udphy->status)
868 return 0;
869
870 udphy->status &= ~mode;
871
872 if (udphy->status == UDPHY_MODE_NONE) {
873 ret = udphy_disable(udphy);
874 if (ret)
875 return ret;
876 }
877
878 return 0;
879 }
880
rockchip_dp_phy_power_on(struct phy * phy)881 static int rockchip_dp_phy_power_on(struct phy *phy)
882 {
883 struct rockchip_udphy *udphy = phy_get_drvdata(phy);
884 int ret, dp_lanes;
885
886 mutex_lock(&udphy->mutex);
887
888 dp_lanes = udphy_dplane_get(udphy);
889 phy_set_bus_width(phy, dp_lanes);
890
891 ret = udphy_power_on(udphy, UDPHY_MODE_DP);
892 if (ret)
893 goto unlock;
894
895 ret = udphy_dplane_enable(udphy, dp_lanes);
896 if (ret)
897 goto unlock;
898
899 ret = udphy_dplane_select(udphy);
900
901 unlock:
902 mutex_unlock(&udphy->mutex);
903 /*
904 * If data send by aux channel too fast after phy power on,
905 * the aux may be not ready which will cause aux error. Adding
906 * delay to avoid this issue.
907 */
908 usleep_range(10000, 11000);
909 return ret;
910 }
911
rockchip_dp_phy_power_off(struct phy * phy)912 static int rockchip_dp_phy_power_off(struct phy *phy)
913 {
914 struct rockchip_udphy *udphy = phy_get_drvdata(phy);
915 int ret;
916
917 mutex_lock(&udphy->mutex);
918 ret = udphy_dplane_enable(udphy, 0);
919 if (ret)
920 goto unlock;
921
922 ret = udphy_power_off(udphy, UDPHY_MODE_DP);
923
924 unlock:
925 mutex_unlock(&udphy->mutex);
926 return ret;
927 }
928
rockchip_dp_phy_verify_link_rate(unsigned int link_rate)929 static int rockchip_dp_phy_verify_link_rate(unsigned int link_rate)
930 {
931 switch (link_rate) {
932 case 1620:
933 case 2700:
934 case 5400:
935 case 8100:
936 break;
937 default:
938 return -EINVAL;
939 }
940
941 return 0;
942 }
943
rockchip_dp_phy_verify_config(struct rockchip_udphy * udphy,struct phy_configure_opts_dp * dp)944 static int rockchip_dp_phy_verify_config(struct rockchip_udphy *udphy,
945 struct phy_configure_opts_dp *dp)
946 {
947 int i, ret;
948
949 /* If changing link rate was required, verify it's supported. */
950 ret = rockchip_dp_phy_verify_link_rate(dp->link_rate);
951 if (ret)
952 return ret;
953
954 /* Verify lane count. */
955 switch (dp->lanes) {
956 case 1:
957 case 2:
958 case 4:
959 /* valid lane count. */
960 break;
961 default:
962 return -EINVAL;
963 }
964
965 /*
966 * If changing voltages is required, check swing and pre-emphasis
967 * levels, per-lane.
968 */
969 if (dp->set_voltages) {
970 /* Lane count verified previously. */
971 for (i = 0; i < dp->lanes; i++) {
972 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
973 return -EINVAL;
974
975 /*
976 * Sum of voltage swing and pre-emphasis levels cannot
977 * exceed 3.
978 */
979 if (dp->voltage[i] + dp->pre[i] > 3)
980 return -EINVAL;
981 }
982 }
983
984 return 0;
985 }
986
rockchip_dp_phy_configure(struct phy * phy,union phy_configure_opts * opts)987 static int rockchip_dp_phy_configure(struct phy *phy,
988 union phy_configure_opts *opts)
989 {
990 struct rockchip_udphy *udphy = phy_get_drvdata(phy);
991 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
992 int ret;
993
994 ret = rockchip_dp_phy_verify_config(udphy, &opts->dp);
995 if (ret)
996 return ret;
997
998 if (opts->dp.set_rate && cfg->dp_phy_set_rate) {
999 ret = cfg->dp_phy_set_rate(udphy, &opts->dp);
1000 if (ret) {
1001 dev_err(udphy->dev,
1002 "rockchip_hdptx_phy_set_rate failed\n");
1003 return ret;
1004 }
1005 }
1006
1007 if (opts->dp.set_voltages && cfg->dp_phy_set_voltages) {
1008 ret = cfg->dp_phy_set_voltages(udphy, &opts->dp);
1009 if (ret) {
1010 dev_err(udphy->dev,
1011 "rockchip_dp_phy_set_voltages failed\n");
1012 return ret;
1013 }
1014 }
1015
1016 return 0;
1017 }
1018
1019 static const struct phy_ops rockchip_dp_phy_ops = {
1020 .power_on = rockchip_dp_phy_power_on,
1021 .power_off = rockchip_dp_phy_power_off,
1022 .configure = rockchip_dp_phy_configure,
1023 .owner = THIS_MODULE,
1024 };
1025
rockchip_u3phy_init(struct phy * phy)1026 static int rockchip_u3phy_init(struct phy *phy)
1027 {
1028 struct rockchip_udphy *udphy = phy_get_drvdata(phy);
1029 int ret = 0;
1030
1031 mutex_lock(&udphy->mutex);
1032 /* DP only or high-speed, disable U3 port */
1033 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
1034 udphy_u3_port_disable(udphy, true);
1035 goto unlock;
1036 }
1037
1038 ret = udphy_power_on(udphy, UDPHY_MODE_USB);
1039
1040 unlock:
1041 mutex_unlock(&udphy->mutex);
1042 return ret;
1043 }
1044
rockchip_u3phy_exit(struct phy * phy)1045 static int rockchip_u3phy_exit(struct phy *phy)
1046 {
1047 struct rockchip_udphy *udphy = phy_get_drvdata(phy);
1048 int ret = 0;
1049
1050 mutex_lock(&udphy->mutex);
1051 /* DP only or high-speed */
1052 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
1053 goto unlock;
1054
1055 ret = udphy_power_off(udphy, UDPHY_MODE_USB);
1056
1057 unlock:
1058 mutex_unlock(&udphy->mutex);
1059 return ret;
1060 }
1061
1062 static const struct phy_ops rockchip_u3phy_ops = {
1063 .init = rockchip_u3phy_init,
1064 .exit = rockchip_u3phy_exit,
1065 .owner = THIS_MODULE,
1066 };
1067
usbdp_typec_mux_set(struct typec_mux * mux,struct typec_mux_state * state)1068 static int usbdp_typec_mux_set(struct typec_mux *mux,
1069 struct typec_mux_state *state)
1070 {
1071 struct rockchip_udphy *udphy = typec_mux_get_drvdata(mux);
1072 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
1073 u8 mode;
1074
1075 mutex_lock(&udphy->mutex);
1076
1077 switch (state->mode) {
1078 case TYPEC_DP_STATE_C:
1079 fallthrough;
1080 case TYPEC_DP_STATE_E:
1081 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
1082 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
1083 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
1084 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
1085 mode = UDPHY_MODE_DP;
1086 break;
1087 case TYPEC_DP_STATE_D:
1088 fallthrough;
1089 default:
1090 if (udphy->flip) {
1091 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
1092 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
1093 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
1094 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
1095 } else {
1096 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
1097 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
1098 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
1099 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
1100 }
1101 mode = UDPHY_MODE_DP_USB;
1102 break;
1103 }
1104
1105 if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) {
1106 struct typec_displayport_data *data = state->data;
1107
1108 if (!data) {
1109 if (cfg->hpd_event_trigger)
1110 cfg->hpd_event_trigger(udphy, false);
1111 } else if (data->status & DP_STATUS_IRQ_HPD) {
1112 if (cfg->hpd_event_trigger) {
1113 cfg->hpd_event_trigger(udphy, false);
1114 usleep_range(750, 800);
1115 cfg->hpd_event_trigger(udphy, true);
1116 }
1117 } else if (data->status & DP_STATUS_HPD_STATE) {
1118 if (udphy->mode != mode) {
1119 udphy->mode = mode;
1120 udphy->mode_change = true;
1121 }
1122 if (cfg->hpd_event_trigger)
1123 cfg->hpd_event_trigger(udphy, true);
1124 } else {
1125 if (cfg->hpd_event_trigger)
1126 cfg->hpd_event_trigger(udphy, false);
1127 }
1128 }
1129
1130 mutex_unlock(&udphy->mutex);
1131 return 0;
1132 }
1133
udphy_setup_typec_mux(struct rockchip_udphy * udphy)1134 static int udphy_setup_typec_mux(struct rockchip_udphy *udphy)
1135 {
1136 struct typec_mux_desc mux_desc = {};
1137
1138 mux_desc.drvdata = udphy;
1139 mux_desc.fwnode = dev_fwnode(udphy->dev);
1140 mux_desc.set = usbdp_typec_mux_set;
1141
1142 udphy->mux = typec_mux_register(udphy->dev, &mux_desc);
1143 if (IS_ERR(udphy->mux)) {
1144 dev_err(udphy->dev, "Error register typec mux: %ld\n",
1145 PTR_ERR(udphy->mux));
1146 return PTR_ERR(udphy->mux);
1147 }
1148
1149 return 0;
1150 }
1151
udphy_typec_mux_unregister(void * data)1152 static void udphy_typec_mux_unregister(void *data)
1153 {
1154 struct rockchip_udphy *udphy = data;
1155
1156 typec_mux_unregister(udphy->mux);
1157 }
1158
udphy_dp_get_max_link_rate(struct rockchip_udphy * udphy,struct device_node * np)1159 static u32 udphy_dp_get_max_link_rate(struct rockchip_udphy *udphy, struct device_node *np)
1160 {
1161 u32 max_link_rate;
1162 int ret;
1163
1164 ret = of_property_read_u32(np, "max-link-rate", &max_link_rate);
1165 if (ret)
1166 return 8100;
1167
1168 ret = rockchip_dp_phy_verify_link_rate(max_link_rate);
1169 if (ret) {
1170 dev_warn(udphy->dev, "invalid max-link-rate value:%d\n", max_link_rate);
1171 max_link_rate = 8100;
1172 }
1173
1174 return max_link_rate;
1175 }
1176
1177 static const struct regmap_config rockchip_udphy_pma_regmap_cfg = {
1178 .reg_bits = 32,
1179 .reg_stride = 4,
1180 .val_bits = 32,
1181 .fast_io = true,
1182 .max_register = 0x20dc,
1183 };
1184
rockchip_udphy_probe(struct platform_device * pdev)1185 static int rockchip_udphy_probe(struct platform_device *pdev)
1186 {
1187 struct device *dev = &pdev->dev;
1188 struct device_node *np = dev->of_node;
1189 struct device_node *child_np;
1190 struct phy_provider *phy_provider;
1191 struct resource *res;
1192 struct rockchip_udphy *udphy;
1193 const struct rockchip_udphy_cfg *phy_cfgs;
1194 void __iomem *base;
1195 int id, ret;
1196
1197 udphy = devm_kzalloc(dev, sizeof(*udphy), GFP_KERNEL);
1198 if (!udphy)
1199 return -ENOMEM;
1200
1201 id = of_alias_get_id(dev->of_node, "usbdp");
1202 if (id < 0)
1203 id = 0;
1204 udphy->id = id;
1205
1206 phy_cfgs = of_device_get_match_data(dev);
1207 if (!phy_cfgs) {
1208 dev_err(dev, "no OF data can be matched with %p node\n", np);
1209 return -EINVAL;
1210 }
1211
1212 udphy->cfgs = phy_cfgs;
1213
1214 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1215 base = devm_ioremap_resource(dev, res);
1216 if (IS_ERR(base))
1217 return PTR_ERR(base);
1218
1219 udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA,
1220 &rockchip_udphy_pma_regmap_cfg);
1221 if (IS_ERR(udphy->pma_regmap))
1222 return PTR_ERR(udphy->pma_regmap);
1223
1224 ret = udphy_parse_dt(udphy, dev);
1225 if (ret)
1226 return ret;
1227
1228 ret = udphy_get_initial_status(udphy);
1229 if (ret)
1230 return ret;
1231
1232 mutex_init(&udphy->mutex);
1233 udphy->dev = dev;
1234 platform_set_drvdata(pdev, udphy);
1235
1236 if (device_property_present(dev, "orientation-switch")) {
1237 ret = udphy_setup_orien_switch(udphy);
1238 if (ret)
1239 return ret;
1240
1241 ret = devm_add_action_or_reset(dev, udphy_orien_switch_unregister, udphy);
1242 if (ret)
1243 return ret;
1244 }
1245
1246 if (device_property_present(dev, "svid")) {
1247 ret = udphy_setup_typec_mux(udphy);
1248 if (ret)
1249 return ret;
1250
1251 ret = devm_add_action_or_reset(dev, udphy_typec_mux_unregister, udphy);
1252 if (ret)
1253 return ret;
1254 }
1255
1256 for_each_available_child_of_node(np, child_np) {
1257 struct phy *phy;
1258
1259 if (of_node_name_eq(child_np, "dp-port")) {
1260 phy = devm_phy_create(dev, child_np, &rockchip_dp_phy_ops);
1261 if (IS_ERR(phy)) {
1262 dev_err(dev, "failed to create dp phy: %pOFn\n", child_np);
1263 goto put_child;
1264 }
1265
1266 phy_set_bus_width(phy, udphy_dplane_get(udphy));
1267 phy->attrs.max_link_rate = udphy_dp_get_max_link_rate(udphy, child_np);
1268 } else if (of_node_name_eq(child_np, "u3-port")) {
1269 phy = devm_phy_create(dev, child_np, &rockchip_u3phy_ops);
1270 if (IS_ERR(phy)) {
1271 dev_err(dev, "failed to create usb phy: %pOFn\n", child_np);
1272 goto put_child;
1273 }
1274 } else
1275 continue;
1276
1277 phy_set_drvdata(phy, udphy);
1278 }
1279
1280 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1281 if (IS_ERR(phy_provider)) {
1282 dev_err(dev, "failed to register phy provider\n");
1283 goto put_child;
1284 }
1285
1286 return 0;
1287
1288 put_child:
1289 of_node_put(child_np);
1290 return ret;
1291 }
1292
rk3588_udphy_refclk_set(struct rockchip_udphy * udphy)1293 static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)
1294 {
1295 unsigned long rate;
1296 int ret;
1297
1298 /* configure phy reference clock */
1299 rate = clk_get_rate(udphy->refclk);
1300 dev_dbg(udphy->dev, "refclk freq %ld\n", rate);
1301
1302 switch (rate) {
1303 case 24000000:
1304 ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_24m_refclk_cfg,
1305 ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg));
1306 if (ret)
1307 return ret;
1308 break;
1309 case 26000000:
1310 /* register default is 26MHz */
1311 ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_26m_refclk_cfg,
1312 ARRAY_SIZE(rk3588_udphy_26m_refclk_cfg));
1313 if (ret)
1314 return ret;
1315 break;
1316 default:
1317 dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate);
1318 return -EINVAL;
1319 }
1320
1321 return 0;
1322 }
1323
rk3588_udphy_status_check(struct rockchip_udphy * udphy)1324 static int rk3588_udphy_status_check(struct rockchip_udphy *udphy)
1325 {
1326 unsigned int val;
1327 int ret;
1328
1329 /* LCPLL check */
1330 if (udphy->mode & UDPHY_MODE_USB) {
1331 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET,
1332 val, (val & CMN_ANA_LCPLL_AFC_DONE) &&
1333 (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000);
1334 if (ret) {
1335 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");
1336 return ret;
1337 }
1338 }
1339
1340 if (udphy->mode & UDPHY_MODE_USB) {
1341 if (!udphy->flip) {
1342 ret = regmap_read_poll_timeout(udphy->pma_regmap,
1343 TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val,
1344 val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
1345 200, 100000);
1346 if (ret)
1347 dev_notice(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
1348 } else {
1349 ret = regmap_read_poll_timeout(udphy->pma_regmap,
1350 TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val,
1351 val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
1352 200, 100000);
1353 if (ret)
1354 dev_notice(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
1355 }
1356 }
1357
1358 return 0;
1359 }
1360
rk3588_udphy_init(struct rockchip_udphy * udphy)1361 static int rk3588_udphy_init(struct rockchip_udphy *udphy)
1362 {
1363 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
1364 int ret;
1365
1366 /* enable rx lfps for usb */
1367 if (udphy->mode & UDPHY_MODE_USB)
1368 grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);
1369
1370 /* Step 1: power on pma and deassert apb rstn */
1371 grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);
1372
1373 udphy_reset_deassert(udphy, "pma_apb");
1374 udphy_reset_deassert(udphy, "pcs_apb");
1375
1376 /* Step 2: set init sequence and phy refclk */
1377 ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_init_sequence,
1378 ARRAY_SIZE(rk3588_udphy_init_sequence));
1379 if (ret) {
1380 dev_err(udphy->dev, "init sequence set error %d\n", ret);
1381 goto assert_apb;
1382 }
1383
1384 ret = rk3588_udphy_refclk_set(udphy);
1385 if (ret) {
1386 dev_err(udphy->dev, "refclk set error %d\n", ret);
1387 goto assert_apb;
1388 }
1389
1390 /* Step 3: configure lane mux */
1391 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,
1392 CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL,
1393 FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) |
1394 FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) |
1395 FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) |
1396 FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) |
1397 FIELD_PREP(CMN_DP_LANE_EN_ALL, 0));
1398
1399 /* Step 4: deassert init rstn and wait for 200ns from datasheet */
1400 if (udphy->mode & UDPHY_MODE_USB)
1401 udphy_reset_deassert(udphy, "init");
1402
1403 if (udphy->mode & UDPHY_MODE_DP) {
1404 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
1405 CMN_DP_INIT_RSTN,
1406 FIELD_PREP(CMN_DP_INIT_RSTN, 0x1));
1407 }
1408
1409 udelay(1);
1410
1411 /* Step 5: deassert cmn/lane rstn */
1412 if (udphy->mode & UDPHY_MODE_USB) {
1413 udphy_reset_deassert(udphy, "cmn");
1414 udphy_reset_deassert(udphy, "lane");
1415 }
1416
1417 /* Step 6: wait for lock done of pll */
1418 ret = rk3588_udphy_status_check(udphy);
1419 if (ret)
1420 goto assert_phy;
1421
1422 return 0;
1423
1424 assert_phy:
1425 udphy_reset_assert(udphy, "init");
1426 udphy_reset_assert(udphy, "cmn");
1427 udphy_reset_assert(udphy, "lane");
1428
1429 assert_apb:
1430 udphy_reset_assert(udphy, "pma_apb");
1431 udphy_reset_assert(udphy, "pcs_apb");
1432 return ret;
1433 }
1434
rk3588_udphy_hpd_event_trigger(struct rockchip_udphy * udphy,bool hpd)1435 static int rk3588_udphy_hpd_event_trigger(struct rockchip_udphy *udphy, bool hpd)
1436 {
1437 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
1438
1439 udphy->dp_sink_hpd_sel = true;
1440 udphy->dp_sink_hpd_cfg = hpd;
1441
1442 grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd);
1443
1444 return 0;
1445 }
1446
rk3588_udphy_dplane_enable(struct rockchip_udphy * udphy,int dp_lanes)1447 static int rk3588_udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes)
1448 {
1449 int i;
1450 u32 val = 0;
1451
1452 for (i = 0; i < dp_lanes; i++)
1453 val |= BIT(udphy->dp_lane_sel[i]);
1454
1455 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL,
1456 FIELD_PREP(CMN_DP_LANE_EN_ALL, val));
1457
1458 if (!dp_lanes)
1459 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
1460 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
1461
1462 return 0;
1463 }
1464
rk3588_udphy_dplane_select(struct rockchip_udphy * udphy)1465 static int rk3588_udphy_dplane_select(struct rockchip_udphy *udphy)
1466 {
1467 u32 value = 0;
1468
1469 switch (udphy->mode) {
1470 case UDPHY_MODE_DP:
1471 value |= 2 << udphy->dp_lane_sel[2] * 2;
1472 value |= 3 << udphy->dp_lane_sel[3] * 2;
1473 fallthrough;
1474 case UDPHY_MODE_DP_USB:
1475 value |= 0 << udphy->dp_lane_sel[0] * 2;
1476 value |= 1 << udphy->dp_lane_sel[1] * 2;
1477 break;
1478 case UDPHY_MODE_USB:
1479 break;
1480 default:
1481 break;
1482 }
1483
1484 regmap_write(udphy->vogrf, udphy->id ? RK3588_GRF_VO0_CON2 : RK3588_GRF_VO0_CON0,
1485 ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) |
1486 FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) |
1487 FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
1488
1489 return 0;
1490 }
1491
rk3588_dp_phy_set_rate(struct rockchip_udphy * udphy,struct phy_configure_opts_dp * dp)1492 static int rk3588_dp_phy_set_rate(struct rockchip_udphy *udphy,
1493 struct phy_configure_opts_dp *dp)
1494 {
1495 u32 val;
1496 int ret;
1497
1498 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
1499 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
1500
1501 switch (dp->link_rate) {
1502 case 1620:
1503 udphy->bw = DP_BW_RBR;
1504 break;
1505 case 2700:
1506 udphy->bw = DP_BW_HBR;
1507 break;
1508 case 5400:
1509 udphy->bw = DP_BW_HBR2;
1510 break;
1511 case 8100:
1512 udphy->bw = DP_BW_HBR3;
1513 break;
1514 default:
1515 return -EINVAL;
1516 }
1517
1518 regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW,
1519 FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw));
1520 regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN,
1521 FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc));
1522 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN,
1523 FIELD_PREP(CMN_DP_CMN_RSTN, 0x1));
1524
1525 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val,
1526 FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) &&
1527 FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val),
1528 0, 1000);
1529 if (ret) {
1530 dev_err(udphy->dev, "ROPLL is not lock\n");
1531 return ret;
1532 }
1533
1534 return 0;
1535 }
1536
rk3588_dp_phy_set_voltage(struct rockchip_udphy * udphy,u8 bw,u32 voltage,u32 pre,u32 lane)1537 static void rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy, u8 bw,
1538 u32 voltage, u32 pre, u32 lane)
1539 {
1540 u32 offset = 0x800 * lane;
1541 u32 val;
1542 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
1543 const struct dp_tx_drv_ctrl (*dp_ctrl)[4];
1544
1545 dp_ctrl = udphy->mux ? cfg->dp_tx_ctrl_cfg_typec[bw] : cfg->dp_tx_ctrl_cfg[bw];
1546 val = dp_ctrl[voltage][pre].trsv_reg0204;
1547 regmap_write(udphy->pma_regmap, 0x0810 + offset, val);
1548
1549 val = dp_ctrl[voltage][pre].trsv_reg0205;
1550 regmap_write(udphy->pma_regmap, 0x0814 + offset, val);
1551
1552 val = dp_ctrl[voltage][pre].trsv_reg0206;
1553 regmap_write(udphy->pma_regmap, 0x0818 + offset, val);
1554
1555 val = dp_ctrl[voltage][pre].trsv_reg0207;
1556 regmap_write(udphy->pma_regmap, 0x081c + offset, val);
1557 }
1558
rk3588_dp_phy_set_voltages(struct rockchip_udphy * udphy,struct phy_configure_opts_dp * dp)1559 static int rk3588_dp_phy_set_voltages(struct rockchip_udphy *udphy,
1560 struct phy_configure_opts_dp *dp)
1561 {
1562 u32 i, lane;
1563
1564 for (i = 0; i < dp->lanes; i++) {
1565 lane = udphy->dp_lane_sel[i];
1566 switch (dp->link_rate) {
1567 case 1620:
1568 case 2700:
1569 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),
1570 LN_ANA_TX_SER_TXCLK_INV,
1571 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV,
1572 udphy->lane_mux_sel[lane]));
1573 break;
1574 case 5400:
1575 case 8100:
1576 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),
1577 LN_ANA_TX_SER_TXCLK_INV,
1578 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0));
1579 break;
1580 }
1581
1582 rk3588_dp_phy_set_voltage(udphy, udphy->bw, dp->voltage[i], dp->pre[i], lane);
1583 }
1584
1585 return 0;
1586 }
1587
udphy_resume(struct device * dev)1588 static int __maybe_unused udphy_resume(struct device *dev)
1589 {
1590 struct rockchip_udphy *udphy = dev_get_drvdata(dev);
1591 const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
1592
1593 if (udphy->dp_sink_hpd_sel)
1594 cfg->hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg);
1595
1596 return 0;
1597 }
1598
1599 static const struct dev_pm_ops udphy_pm_ops = {
1600 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, udphy_resume)
1601 };
1602
1603 static const char * const rk3588_udphy_rst_l[] = {
1604 "init", "cmn", "lane", "pcs_apb", "pma_apb"
1605 };
1606
1607 static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
1608 .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
1609 .rst_list = rk3588_udphy_rst_l,
1610 .grfcfg = {
1611 /* u2phy-grf */
1612 .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 },
1613 .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 },
1614
1615 /* usb-grf */
1616 .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 },
1617 .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 },
1618
1619 /* usbdpphy-grf */
1620 .low_pwrn = { 0x0004, 13, 13, 0, 1 },
1621 .rx_lfps = { 0x0004, 14, 14, 0, 1 },
1622 },
1623 .vogrfcfg = {
1624 {
1625 .hpd_trigger = { 0x0000, 11, 10, 1, 3 },
1626 },
1627 {
1628 .hpd_trigger = { 0x0008, 11, 10, 1, 3 },
1629 },
1630 },
1631 .dp_tx_ctrl_cfg = {
1632 rk3588_dp_tx_drv_ctrl_rbr_hbr,
1633 rk3588_dp_tx_drv_ctrl_rbr_hbr,
1634 rk3588_dp_tx_drv_ctrl_hbr2,
1635 rk3588_dp_tx_drv_ctrl_hbr3,
1636 },
1637 .dp_tx_ctrl_cfg_typec = {
1638 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
1639 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
1640 rk3588_dp_tx_drv_ctrl_hbr2,
1641 rk3588_dp_tx_drv_ctrl_hbr3,
1642 },
1643 .combophy_init = rk3588_udphy_init,
1644 .dp_phy_set_rate = rk3588_dp_phy_set_rate,
1645 .dp_phy_set_voltages = rk3588_dp_phy_set_voltages,
1646 .hpd_event_trigger = rk3588_udphy_hpd_event_trigger,
1647 .dplane_enable = rk3588_udphy_dplane_enable,
1648 .dplane_select = rk3588_udphy_dplane_select,
1649 };
1650
1651 static const struct of_device_id rockchip_udphy_dt_match[] = {
1652 {
1653 .compatible = "rockchip,rk3588-usbdp-phy",
1654 .data = &rk3588_udphy_cfgs
1655 },
1656 { /* sentinel */ }
1657 };
1658
1659 MODULE_DEVICE_TABLE(of, rockchip_udphy_dt_match);
1660
1661 static struct platform_driver rockchip_udphy_driver = {
1662 .probe = rockchip_udphy_probe,
1663 .driver = {
1664 .name = "rockchip-usbdp-phy",
1665 .of_match_table = rockchip_udphy_dt_match,
1666 .pm = &udphy_pm_ops,
1667 },
1668 };
1669
1670 module_platform_driver(rockchip_udphy_driver);
1671
1672 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1673 MODULE_AUTHOR("Zhang Yubing <yubing.zhang@rock-chips.com>");
1674 MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver");
1675 MODULE_LICENSE("GPL v2");
1676