Lines Matching +full:dp +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
10 #include <generic-phy.h>
86 { {0x3, 0x1, 0x0}, {0x5, 0x1, 0x7}, {0x6, 0x1, 0x6}, { -1, -1, -1} },
87 { {0x5, 0x1, 0x0}, {0x7, 0x1, 0x4}, { -1, -1, -1}, { -1, -1, -1} },
88 { {0x7, 0x1, 0x0}, { -1, -1, -1}, { -1, -1, -1}, { -1, -1, -1} },
92 struct phy_configure_opts_dp *dp, in rockchip_edp_phy_set_voltage() argument
97 amp = vp[dp->voltage[lane]][dp->pre[lane]].amp; in rockchip_edp_phy_set_voltage()
98 amp_scale = vp[dp->voltage[lane]][dp->pre[lane]].amp_scale; in rockchip_edp_phy_set_voltage()
99 emp = vp[dp->voltage[lane]][dp->pre[lane]].emp; in rockchip_edp_phy_set_voltage()
103 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, in rockchip_edp_phy_set_voltage()
106 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4, in rockchip_edp_phy_set_voltage()
109 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, in rockchip_edp_phy_set_voltage()
114 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, in rockchip_edp_phy_set_voltage()
117 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4, in rockchip_edp_phy_set_voltage()
120 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, in rockchip_edp_phy_set_voltage()
125 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, in rockchip_edp_phy_set_voltage()
128 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4, in rockchip_edp_phy_set_voltage()
131 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, in rockchip_edp_phy_set_voltage()
136 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, in rockchip_edp_phy_set_voltage()
139 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4, in rockchip_edp_phy_set_voltage()
142 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, in rockchip_edp_phy_set_voltage()
150 struct phy_configure_opts_dp *dp) in rockchip_edp_phy_set_voltages() argument
155 for (lane = 0; lane < dp->lanes; lane++) in rockchip_edp_phy_set_voltages()
156 rockchip_edp_phy_set_voltage(edpphy, dp, lane); in rockchip_edp_phy_set_voltages()
162 struct phy_configure_opts_dp *dp) in rockchip_edp_phy_set_rate() argument
167 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, in rockchip_edp_phy_set_rate()
172 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE, in rockchip_edp_phy_set_rate()
174 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL, in rockchip_edp_phy_set_rate()
177 switch (dp->link_rate) { in rockchip_edp_phy_set_rate()
179 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON1, in rockchip_edp_phy_set_rate()
182 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON2, in rockchip_edp_phy_set_rate()
187 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON8, in rockchip_edp_phy_set_rate()
190 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON9, in rockchip_edp_phy_set_rate()
195 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON1, in rockchip_edp_phy_set_rate()
198 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON2, in rockchip_edp_phy_set_rate()
203 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON8, in rockchip_edp_phy_set_rate()
206 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON9, in rockchip_edp_phy_set_rate()
212 if (dp->ssc) in rockchip_edp_phy_set_rate()
213 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON6, in rockchip_edp_phy_set_rate()
219 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON6, in rockchip_edp_phy_set_rate()
223 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL, in rockchip_edp_phy_set_rate()
225 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_TX_PD, in rockchip_edp_phy_set_rate()
226 FIELD_PREP(EDP_PHY_TX_PD, ~GENMASK(dp->lanes - 1, 0))); in rockchip_edp_phy_set_rate()
227 ret = regmap_read_poll_timeout(edpphy->grf, EDP_PHY_GRF_STATUS0, in rockchip_edp_phy_set_rate()
230 dev_err(edpphy->dev, "pll is not ready: %d\n", ret); in rockchip_edp_phy_set_rate()
234 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE, in rockchip_edp_phy_set_rate()
236 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_TX_IDLE, in rockchip_edp_phy_set_rate()
237 FIELD_PREP(EDP_PHY_TX_IDLE, ~GENMASK(dp->lanes - 1, 0))); in rockchip_edp_phy_set_rate()
243 struct phy_configure_opts_dp *dp) in rockchip_edp_phy_verify_config() argument
248 if (dp->set_rate) { in rockchip_edp_phy_verify_config()
249 switch (dp->link_rate) { in rockchip_edp_phy_verify_config()
255 return -EINVAL; in rockchip_edp_phy_verify_config()
260 switch (dp->lanes) { in rockchip_edp_phy_verify_config()
267 return -EINVAL; in rockchip_edp_phy_verify_config()
271 * If changing voltages is required, check swing and pre-emphasis in rockchip_edp_phy_verify_config()
272 * levels, per-lane. in rockchip_edp_phy_verify_config()
274 if (dp->set_voltages) { in rockchip_edp_phy_verify_config()
276 for (i = 0; i < dp->lanes; i++) { in rockchip_edp_phy_verify_config()
277 if (dp->voltage[i] > 3 || dp->pre[i] > 3) in rockchip_edp_phy_verify_config()
278 return -EINVAL; in rockchip_edp_phy_verify_config()
281 * Sum of voltage swing and pre-emphasis levels cannot in rockchip_edp_phy_verify_config()
284 if (dp->voltage[i] + dp->pre[i] > 3) in rockchip_edp_phy_verify_config()
285 return -EINVAL; in rockchip_edp_phy_verify_config()
292 static int rockchip_edp_phy_configure(struct phy *phy, in rockchip_edp_phy_configure() argument
295 struct rockchip_edp_phy *edpphy = dev_get_priv(phy->dev); in rockchip_edp_phy_configure()
298 ret = rockchip_edp_phy_verify_config(edpphy, &opts->dp); in rockchip_edp_phy_configure()
300 dev_err(edpphy->dev, "invalid params for phy configure\n"); in rockchip_edp_phy_configure()
304 if (opts->dp.set_rate) { in rockchip_edp_phy_configure()
305 ret = rockchip_edp_phy_set_rate(edpphy, &opts->dp); in rockchip_edp_phy_configure()
307 dev_err(edpphy->dev, in rockchip_edp_phy_configure()
313 if (opts->dp.set_voltages) { in rockchip_edp_phy_configure()
314 ret = rockchip_edp_phy_set_voltages(edpphy, &opts->dp); in rockchip_edp_phy_configure()
316 dev_err(edpphy->dev, in rockchip_edp_phy_configure()
325 static int rockchip_edp_phy_power_on(struct phy *phy) in rockchip_edp_phy_power_on() argument
327 struct rockchip_edp_phy *edpphy = dev_get_priv(phy->dev); in rockchip_edp_phy_power_on()
329 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10, in rockchip_edp_phy_power_on()
334 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, in rockchip_edp_phy_power_on()
341 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON11, in rockchip_edp_phy_power_on()
351 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10, in rockchip_edp_phy_power_on()
357 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10, in rockchip_edp_phy_power_on()
365 static int rockchip_edp_phy_power_off(struct phy *phy) in rockchip_edp_phy_power_off() argument
367 struct rockchip_edp_phy *edpphy = dev_get_priv(phy->dev); in rockchip_edp_phy_power_off()
369 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, in rockchip_edp_phy_power_off()
374 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE, in rockchip_edp_phy_power_off()
376 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL, in rockchip_edp_phy_power_off()
378 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10, in rockchip_edp_phy_power_off()
402 edpphy->grf = syscon_get_regmap(dev); in rockchip_edp_phy_probe()
403 if (!edpphy->grf){ in rockchip_edp_phy_probe()
405 return -ENOENT; in rockchip_edp_phy_probe()
408 edpphy->dev = dev; in rockchip_edp_phy_probe()
414 { .compatible = "rockchip,rk3568-edp-phy", },