1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#" 5*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Cadence MHDP8546 bridge 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Swapnil Jakhade <sjakhade@cadence.com> 11*4882a593Smuzhiyun - Yuti Amonkar <yamonkar@cadence.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun compatible: 15*4882a593Smuzhiyun enum: 16*4882a593Smuzhiyun - cdns,mhdp8546 17*4882a593Smuzhiyun - ti,j721e-mhdp8546 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun reg: 20*4882a593Smuzhiyun minItems: 1 21*4882a593Smuzhiyun maxItems: 2 22*4882a593Smuzhiyun items: 23*4882a593Smuzhiyun - description: 24*4882a593Smuzhiyun Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P). 25*4882a593Smuzhiyun The AUX and PMA registers are not part of this range, they are instead 26*4882a593Smuzhiyun included in the associated PHY. 27*4882a593Smuzhiyun - description: 28*4882a593Smuzhiyun Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun reg-names: 31*4882a593Smuzhiyun minItems: 1 32*4882a593Smuzhiyun maxItems: 2 33*4882a593Smuzhiyun items: 34*4882a593Smuzhiyun - const: mhdptx 35*4882a593Smuzhiyun - const: j721e-intg 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun clocks: 38*4882a593Smuzhiyun maxItems: 1 39*4882a593Smuzhiyun description: 40*4882a593Smuzhiyun DP bridge clock, used by the IP to know how to translate a number of 41*4882a593Smuzhiyun clock cycles into a time (which is used to comply with DP standard timings 42*4882a593Smuzhiyun and delays). 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun phys: 45*4882a593Smuzhiyun maxItems: 1 46*4882a593Smuzhiyun description: 47*4882a593Smuzhiyun phandle to the DisplayPort PHY. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun phy-names: 50*4882a593Smuzhiyun items: 51*4882a593Smuzhiyun - const: dpphy 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun power-domains: 54*4882a593Smuzhiyun maxItems: 1 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun interrupts: 57*4882a593Smuzhiyun maxItems: 1 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun ports: 60*4882a593Smuzhiyun type: object 61*4882a593Smuzhiyun description: 62*4882a593Smuzhiyun Ports as described in Documentation/devicetree/bindings/graph.txt. 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun properties: 65*4882a593Smuzhiyun '#address-cells': 66*4882a593Smuzhiyun const: 1 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun '#size-cells': 69*4882a593Smuzhiyun const: 0 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun port@0: 72*4882a593Smuzhiyun type: object 73*4882a593Smuzhiyun description: 74*4882a593Smuzhiyun First input port representing the DP bridge input. 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun port@1: 77*4882a593Smuzhiyun type: object 78*4882a593Smuzhiyun description: 79*4882a593Smuzhiyun Second input port representing the DP bridge input. 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun port@2: 82*4882a593Smuzhiyun type: object 83*4882a593Smuzhiyun description: 84*4882a593Smuzhiyun Third input port representing the DP bridge input. 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun port@3: 87*4882a593Smuzhiyun type: object 88*4882a593Smuzhiyun description: 89*4882a593Smuzhiyun Fourth input port representing the DP bridge input. 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun port@4: 92*4882a593Smuzhiyun type: object 93*4882a593Smuzhiyun description: 94*4882a593Smuzhiyun Output port representing the DP bridge output. 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun required: 97*4882a593Smuzhiyun - port@0 98*4882a593Smuzhiyun - port@4 99*4882a593Smuzhiyun - '#address-cells' 100*4882a593Smuzhiyun - '#size-cells' 101*4882a593Smuzhiyun 102*4882a593SmuzhiyunallOf: 103*4882a593Smuzhiyun - if: 104*4882a593Smuzhiyun properties: 105*4882a593Smuzhiyun compatible: 106*4882a593Smuzhiyun contains: 107*4882a593Smuzhiyun const: ti,j721e-mhdp8546 108*4882a593Smuzhiyun then: 109*4882a593Smuzhiyun properties: 110*4882a593Smuzhiyun reg: 111*4882a593Smuzhiyun minItems: 2 112*4882a593Smuzhiyun reg-names: 113*4882a593Smuzhiyun minItems: 2 114*4882a593Smuzhiyun else: 115*4882a593Smuzhiyun properties: 116*4882a593Smuzhiyun reg: 117*4882a593Smuzhiyun maxItems: 1 118*4882a593Smuzhiyun reg-names: 119*4882a593Smuzhiyun maxItems: 1 120*4882a593Smuzhiyun 121*4882a593Smuzhiyunrequired: 122*4882a593Smuzhiyun - compatible 123*4882a593Smuzhiyun - clocks 124*4882a593Smuzhiyun - reg 125*4882a593Smuzhiyun - reg-names 126*4882a593Smuzhiyun - phys 127*4882a593Smuzhiyun - phy-names 128*4882a593Smuzhiyun - interrupts 129*4882a593Smuzhiyun - ports 130*4882a593Smuzhiyun 131*4882a593SmuzhiyunadditionalProperties: false 132*4882a593Smuzhiyun 133*4882a593Smuzhiyunexamples: 134*4882a593Smuzhiyun - | 135*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 136*4882a593Smuzhiyun bus { 137*4882a593Smuzhiyun #address-cells = <2>; 138*4882a593Smuzhiyun #size-cells = <2>; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun mhdp: dp-bridge@f0fb000000 { 141*4882a593Smuzhiyun compatible = "cdns,mhdp8546"; 142*4882a593Smuzhiyun reg = <0xf0 0xfb000000 0x0 0x1000000>; 143*4882a593Smuzhiyun reg-names = "mhdptx"; 144*4882a593Smuzhiyun clocks = <&mhdp_clock>; 145*4882a593Smuzhiyun phys = <&dp_phy>; 146*4882a593Smuzhiyun phy-names = "dpphy"; 147*4882a593Smuzhiyun interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun ports { 150*4882a593Smuzhiyun #address-cells = <1>; 151*4882a593Smuzhiyun #size-cells = <0>; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun port@0 { 154*4882a593Smuzhiyun reg = <0>; 155*4882a593Smuzhiyun dp_bridge_input: endpoint { 156*4882a593Smuzhiyun remote-endpoint = <&xxx_dpi_output>; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun port@4 { 161*4882a593Smuzhiyun reg = <4>; 162*4882a593Smuzhiyun dp_bridge_output: endpoint { 163*4882a593Smuzhiyun remote-endpoint = <&xxx_dp_connector_input>; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun... 170