1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyunccflags-y := -I $(srctree)/$(src) 3*4882a593Smuzhiyunccflags-y += -I $(srctree)/$(src)/disp/dpu1 4*4882a593Smuzhiyunccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi 5*4882a593Smuzhiyunccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp 6*4882a593Smuzhiyun 7*4882a593Smuzhiyunmsm-y := \ 8*4882a593Smuzhiyun adreno/adreno_device.o \ 9*4882a593Smuzhiyun adreno/adreno_gpu.o \ 10*4882a593Smuzhiyun adreno/a2xx_gpu.o \ 11*4882a593Smuzhiyun adreno/a3xx_gpu.o \ 12*4882a593Smuzhiyun adreno/a4xx_gpu.o \ 13*4882a593Smuzhiyun adreno/a5xx_gpu.o \ 14*4882a593Smuzhiyun adreno/a5xx_power.o \ 15*4882a593Smuzhiyun adreno/a5xx_preempt.o \ 16*4882a593Smuzhiyun adreno/a6xx_gpu.o \ 17*4882a593Smuzhiyun adreno/a6xx_gmu.o \ 18*4882a593Smuzhiyun adreno/a6xx_hfi.o \ 19*4882a593Smuzhiyun hdmi/hdmi.o \ 20*4882a593Smuzhiyun hdmi/hdmi_audio.o \ 21*4882a593Smuzhiyun hdmi/hdmi_bridge.o \ 22*4882a593Smuzhiyun hdmi/hdmi_connector.o \ 23*4882a593Smuzhiyun hdmi/hdmi_i2c.o \ 24*4882a593Smuzhiyun hdmi/hdmi_phy.o \ 25*4882a593Smuzhiyun hdmi/hdmi_phy_8960.o \ 26*4882a593Smuzhiyun hdmi/hdmi_phy_8x60.o \ 27*4882a593Smuzhiyun hdmi/hdmi_phy_8x74.o \ 28*4882a593Smuzhiyun edp/edp.o \ 29*4882a593Smuzhiyun edp/edp_aux.o \ 30*4882a593Smuzhiyun edp/edp_bridge.o \ 31*4882a593Smuzhiyun edp/edp_connector.o \ 32*4882a593Smuzhiyun edp/edp_ctrl.o \ 33*4882a593Smuzhiyun edp/edp_phy.o \ 34*4882a593Smuzhiyun disp/mdp_format.o \ 35*4882a593Smuzhiyun disp/mdp_kms.o \ 36*4882a593Smuzhiyun disp/mdp4/mdp4_crtc.o \ 37*4882a593Smuzhiyun disp/mdp4/mdp4_dtv_encoder.o \ 38*4882a593Smuzhiyun disp/mdp4/mdp4_lcdc_encoder.o \ 39*4882a593Smuzhiyun disp/mdp4/mdp4_lvds_connector.o \ 40*4882a593Smuzhiyun disp/mdp4/mdp4_irq.o \ 41*4882a593Smuzhiyun disp/mdp4/mdp4_kms.o \ 42*4882a593Smuzhiyun disp/mdp4/mdp4_plane.o \ 43*4882a593Smuzhiyun disp/mdp5/mdp5_cfg.o \ 44*4882a593Smuzhiyun disp/mdp5/mdp5_ctl.o \ 45*4882a593Smuzhiyun disp/mdp5/mdp5_crtc.o \ 46*4882a593Smuzhiyun disp/mdp5/mdp5_encoder.o \ 47*4882a593Smuzhiyun disp/mdp5/mdp5_irq.o \ 48*4882a593Smuzhiyun disp/mdp5/mdp5_mdss.o \ 49*4882a593Smuzhiyun disp/mdp5/mdp5_kms.o \ 50*4882a593Smuzhiyun disp/mdp5/mdp5_pipe.o \ 51*4882a593Smuzhiyun disp/mdp5/mdp5_mixer.o \ 52*4882a593Smuzhiyun disp/mdp5/mdp5_plane.o \ 53*4882a593Smuzhiyun disp/mdp5/mdp5_smp.o \ 54*4882a593Smuzhiyun disp/dpu1/dpu_core_irq.o \ 55*4882a593Smuzhiyun disp/dpu1/dpu_core_perf.o \ 56*4882a593Smuzhiyun disp/dpu1/dpu_crtc.o \ 57*4882a593Smuzhiyun disp/dpu1/dpu_encoder.o \ 58*4882a593Smuzhiyun disp/dpu1/dpu_encoder_phys_cmd.o \ 59*4882a593Smuzhiyun disp/dpu1/dpu_encoder_phys_vid.o \ 60*4882a593Smuzhiyun disp/dpu1/dpu_formats.o \ 61*4882a593Smuzhiyun disp/dpu1/dpu_hw_blk.o \ 62*4882a593Smuzhiyun disp/dpu1/dpu_hw_catalog.o \ 63*4882a593Smuzhiyun disp/dpu1/dpu_hw_ctl.o \ 64*4882a593Smuzhiyun disp/dpu1/dpu_hw_interrupts.o \ 65*4882a593Smuzhiyun disp/dpu1/dpu_hw_intf.o \ 66*4882a593Smuzhiyun disp/dpu1/dpu_hw_lm.o \ 67*4882a593Smuzhiyun disp/dpu1/dpu_hw_pingpong.o \ 68*4882a593Smuzhiyun disp/dpu1/dpu_hw_sspp.o \ 69*4882a593Smuzhiyun disp/dpu1/dpu_hw_dspp.o \ 70*4882a593Smuzhiyun disp/dpu1/dpu_hw_top.o \ 71*4882a593Smuzhiyun disp/dpu1/dpu_hw_util.o \ 72*4882a593Smuzhiyun disp/dpu1/dpu_hw_vbif.o \ 73*4882a593Smuzhiyun disp/dpu1/dpu_io_util.o \ 74*4882a593Smuzhiyun disp/dpu1/dpu_kms.o \ 75*4882a593Smuzhiyun disp/dpu1/dpu_mdss.o \ 76*4882a593Smuzhiyun disp/dpu1/dpu_plane.o \ 77*4882a593Smuzhiyun disp/dpu1/dpu_rm.o \ 78*4882a593Smuzhiyun disp/dpu1/dpu_vbif.o \ 79*4882a593Smuzhiyun msm_atomic.o \ 80*4882a593Smuzhiyun msm_atomic_tracepoints.o \ 81*4882a593Smuzhiyun msm_debugfs.o \ 82*4882a593Smuzhiyun msm_drv.o \ 83*4882a593Smuzhiyun msm_fb.o \ 84*4882a593Smuzhiyun msm_fence.o \ 85*4882a593Smuzhiyun msm_gem.o \ 86*4882a593Smuzhiyun msm_gem_prime.o \ 87*4882a593Smuzhiyun msm_gem_shrinker.o \ 88*4882a593Smuzhiyun msm_gem_submit.o \ 89*4882a593Smuzhiyun msm_gem_vma.o \ 90*4882a593Smuzhiyun msm_gpu.o \ 91*4882a593Smuzhiyun msm_iommu.o \ 92*4882a593Smuzhiyun msm_perf.o \ 93*4882a593Smuzhiyun msm_rd.o \ 94*4882a593Smuzhiyun msm_ringbuffer.o \ 95*4882a593Smuzhiyun msm_submitqueue.o \ 96*4882a593Smuzhiyun msm_gpu_tracepoints.o \ 97*4882a593Smuzhiyun msm_gpummu.o 98*4882a593Smuzhiyun 99*4882a593Smuzhiyunmsm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \ 100*4882a593Smuzhiyun dp/dp_debug.o 101*4882a593Smuzhiyun 102*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o 103*4882a593Smuzhiyun 104*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \ 105*4882a593Smuzhiyun dp/dp_catalog.o \ 106*4882a593Smuzhiyun dp/dp_ctrl.o \ 107*4882a593Smuzhiyun dp/dp_display.o \ 108*4882a593Smuzhiyun dp/dp_drm.o \ 109*4882a593Smuzhiyun dp/dp_hpd.o \ 110*4882a593Smuzhiyun dp/dp_link.o \ 111*4882a593Smuzhiyun dp/dp_panel.o \ 112*4882a593Smuzhiyun dp/dp_parser.o \ 113*4882a593Smuzhiyun dp/dp_power.o \ 114*4882a593Smuzhiyun dp/dp_audio.o 115*4882a593Smuzhiyun 116*4882a593Smuzhiyunmsm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o 117*4882a593Smuzhiyunmsm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o 118*4882a593Smuzhiyunmsm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o 119*4882a593Smuzhiyunmsm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_phy_8996.o 120*4882a593Smuzhiyun 121*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o 122*4882a593Smuzhiyun 123*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ 124*4882a593Smuzhiyun disp/mdp4/mdp4_dsi_encoder.o \ 125*4882a593Smuzhiyun dsi/dsi_cfg.o \ 126*4882a593Smuzhiyun dsi/dsi_host.o \ 127*4882a593Smuzhiyun dsi/dsi_manager.o \ 128*4882a593Smuzhiyun dsi/phy/dsi_phy.o \ 129*4882a593Smuzhiyun disp/mdp5/mdp5_cmd_encoder.o 130*4882a593Smuzhiyun 131*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o 132*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o 133*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o 134*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o 135*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o 136*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o 137*4882a593Smuzhiyun 138*4882a593Smuzhiyunifeq ($(CONFIG_DRM_MSM_DSI_PLL),y) 139*4882a593Smuzhiyunmsm-y += dsi/pll/dsi_pll.o 140*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o 141*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o 142*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/pll/dsi_pll_14nm.o 143*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/pll/dsi_pll_10nm.o 144*4882a593Smuzhiyunmsm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/pll/dsi_pll_7nm.o 145*4882a593Smuzhiyunendif 146*4882a593Smuzhiyun 147*4882a593Smuzhiyunobj-$(CONFIG_DRM_MSM) += msm.o 148