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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dimx7ulp.dtsi2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
9 #include <dt-bindings/clock/imx7ulp-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/gpio/gpio.h>
13 #include "imx7ulp-pinfunc.h"
16 interrupt-parent = <&intc>;
37 #address-cells = <1>;
38 #size-cells = <0>;
41 compatible = "arm,cortex-a7";
47 reserved-memory {
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/img/
H A Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/msm/
H A Ddpu.txt6 sub-blocks like DPU display controller, DSI and DP interfaces etc.
11 - compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
12 - reg: physical base address and length of contoller's registers.
13 - reg-names: register region names. The following region is required:
15 - power-domains: a power domain consumer specifier according to
17 - clocks: list of clock specifiers for clocks needed by the device.
18 - clock-names: device clock names, must be in same order as clocks property.
23 - interrupts: interrupt signal from MDSS.
24 - interrupt-controller: identifies the node as an interrupt controller.
25 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx7ulp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
[all …]
H A Dexynos4412-odroid-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
17 stdout-path = &serial_1;
21 compatible = "samsung,secure-firmware";
[all …]
H A Dimx7d-zii-rpu2.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * RPU - Remote Peripheral Unit
10 /dts-v1/;
11 #include <dt-bindings/thermal/thermal.h>
16 compatible = "zii,imx7d-rpu2", "fsl,imx7d";
19 stdout-path = &uart2;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <24576000>;
28 cs2000_in_dummy: dummy-oscillator {
[all …]
H A Dimx7d-sdb.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 /dts-v1/;
11 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
14 stdout-path = &uart1;
22 gpio-keys {
23 compatible = "gpio-keys";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_gpio_keys>;
27 volume-up {
31 wakeup-source;
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra210-ahub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 for audio pre-processing, post-processing and a programmable full
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^ahub@[0-9a-f]*$"
26 - enum:
27 - nvidia,tegra210-ahub
[all …]
H A Dnvidia,tegra186-dspk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra186-dspk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 Density Modulation (PDM) transmitter that up-samples the input to
13 over sampled Pulse Code Modulation (PCM) input to the desired 1-bit
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^dspk@[0-9a-f]*$"
26 - const: nvidia,tegra186-dspk
[all …]
H A Dnvidia,tegra210-dmic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-dmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
21 pattern: "^dmic@[0-9a-f]*$"
25 - const: nvidia,tegra210-dmic
26 - items:
27 - enum:
[all …]
H A Dnvidia,tegra210-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Inter-IC Sound (I2S) controller implements full-duplex,
11 bi-directional and single direction point-to-point serial
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
21 pattern: "^i2s@[0-9a-f]*$"
25 - const: nvidia,tegra210-i2s
[all …]
H A Dbrcm,cygnus-audio.txt4 - compatible : "brcm,cygnus-audio"
5 - #address-cells: 32bit valued, 1 cell.
6 - #size-cells: 32bit valued, 0 cell.
7 - reg : Should contain audio registers location and length
8 - reg-names: names of the registers listed in "reg" property
12 - clocks: PLL and leaf clocks used by audio ports
13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
[all …]
H A Dmt2701-afe-pcm.txt4 - compatible: should be one of the followings.
5 - "mediatek,mt2701-audio"
6 - "mediatek,mt7622-audio"
7 - interrupts: should contain AFE and ASYS interrupts
8 - interrupt-names: should be "afe" and "asys"
9 - power-domains: should define the power domain
10 - clocks: Must contain an entry for each entry in clock-names
11 See ../clocks/clock-bindings.txt for details
12 - clock-names: should have these clock names:
47 - assigned-clocks: list of input clocks and dividers for the audio system.
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/rng/
H A Drockchip,rng.txt5 - compatible : should be one of the following.
6 "rockchip,cryptov1-rng" for crypto v1
7 "rockchip,cryptov2-rng" for crypto v2
9 - reg : Specifies base physical address and size of the registers map.
10 - clocks : Phandle to clock-controller plus clock-specifier pair.
11 - clock-names : "clk_crypto", "clk_crypto_apk", "aclk_crypto", "hclk_crypto" as a clock name.
12 - assigned-clocks: Main clock, should be <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
14 - assigned-clock-rates : The rng core clk frequency, shall be: <150000000>, <150000000>,
16 - resets : Used for module reset
17 - reset-names : Reset names, should be "reset"
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dclock-bindings.txt1 This binding is a work-in-progress, and are based on some experimental
4 Sources of clock signal can be represented by any node in the device
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs. Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device. The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
14 ==Clock providers==
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/hisilicon/
H A Dhisi-ade.txt1 Device-Tree bindings for hisilicon ADE display controller driver
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
16 "clk_ade_core" for the ADE core clock.
[all …]
/OK3568_Linux_fs/u-boot/drivers/clk/
H A Dclk-uclass.c7 * SPDX-License-Identifier: GPL-2.0+
12 #include <clk-uclass.h>
14 #include <dm/device-internal.h>
16 #include <dt-structs.h>
21 return (const struct clk_ops *)dev->driver->ops; in clk_dev_ops()
32 return -ENOSYS; in clk_get_by_index_platdata()
33 ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev); in clk_get_by_index_platdata()
36 clk->id = cells[0].arg[0]; in clk_get_by_index_platdata()
46 if (args->args_count > 1) { in clk_of_xlate_default()
47 debug("Invaild args_count: %d\n", args->args_count); in clk_of_xlate_default()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-conf.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
9 #include <linux/clk/clk-conf.h>
20 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
21 "#clock-cells"); in __set_clk_parents()
22 if (num_parents == -EINVAL) in __set_clk_parents()
23 pr_err("clk: invalid value of clock-parents property at %pOF\n", in __set_clk_parents()
27 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
28 "#clock-cells", index, &clkspec); in __set_clk_parents()
31 if (rc == -ENOENT) in __set_clk_parents()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mq-pinfunc.h"
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Dpx30-ad-r35-mb-rk618-hdmi.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/clock/rk618-cru.h>
8 #include "px30-ad-r35-mb.dtsi"
11 auto-freq-en = <0>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&i2s1_2ch_mclk>;
23 clock-names = "clkin";
24 assigned-clocks = <&cru SCLK_I2S1_OUT>;
25 assigned-clock-rates = <11289600>;
[all …]
H A Drk3568-nvr-demo-v10.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "rk3568-nvr.dtsi"
10 #include <dt-bindings/clock/rk618-cru.h>
14 compatible = "rockchip,rk3568-nvr-demo-v10", "rockchip,rk3568";
16 gpio-leds {
17 compatible = "gpio-leds";
19 hdd-led {
21 default-state = "off";
23 net-led {
[all …]
H A Drk3399-vop-clk-set.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 assigned-clocks = <&cru SCLK_EMMC>;
17 assigned-clock-parents = <&cru PLL_GPLL>;
18 assigned-clock-rates = <200000000>;
22 assigned-clocks = <&cru SCLK_UART0_SRC>;
23 assigned-clock-parents = <&cru PLL_GPLL>;
27 assigned-clocks = <&cru SCLK_UART_SRC>;
28 assigned-clock-parents = <&cru PLL_GPLL>;
32 assigned-clocks = <&cru SCLK_UART_SRC>;
33 assigned-clock-parents = <&cru PLL_GPLL>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Dvf610-nfc.txt7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
16 clock are found in the SoC hardware reference manual. Furthermore,
17 there might be restrictions on maximum rates when using hardware ECC.
19 - #address-cells, #size-cells : Must be present if the device has sub-nodes
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/ata/
H A Dqcom-sata.txt3 SATA nodes are defined to describe on-chip Serial ATA controllers.
7 - compatible : compatible list, must contain "generic-ahci"
8 - interrupts : <interrupt mapping for SATA IRQ>
9 - reg : <registers mapping>
10 - phys : Must contain exactly one entry as specified
11 in phy-bindings.txt
12 - phy-names : Must be "sata-phy"
14 Required properties for "qcom,ipq806x-ahci" compatible:
15 - clocks : Must contain an entry for each entry in clock-names.
16 - clock-names : Shall be:
[all …]

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