1*4882a593SmuzhiyunDevice-Tree bindings for hisilicon ADE display controller driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunADE (Advanced Display Engine) is the display controller which grab image 4*4882a593Smuzhiyundata from memory, do composition, do post image processing, generate RGB 5*4882a593Smuzhiyuntiming stream and transfer to DSI. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: value should be "hisilicon,hi6220-ade". 9*4882a593Smuzhiyun- reg: physical base address and length of the ADE controller's registers. 10*4882a593Smuzhiyun- hisilicon,noc-syscon: ADE NOC QoS syscon. 11*4882a593Smuzhiyun- resets: The ADE reset controller node. 12*4882a593Smuzhiyun- interrupt: the ldi vblank interrupt number used. 13*4882a593Smuzhiyun- clocks: a list of phandle + clock-specifier pairs, one for each entry 14*4882a593Smuzhiyun in clock-names. 15*4882a593Smuzhiyun- clock-names: should contain: 16*4882a593Smuzhiyun "clk_ade_core" for the ADE core clock. 17*4882a593Smuzhiyun "clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with 18*4882a593Smuzhiyun jpeg codec. 19*4882a593Smuzhiyun "clk_ade_pix" for the ADE pixel clock. 20*4882a593Smuzhiyun- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks' 21*4882a593Smuzhiyun phandle + clock-specifier pairs. 22*4882a593Smuzhiyun- assigned-clock-rates: clock rates, one for each entry in assigned-clocks. 23*4882a593Smuzhiyun The rate of "clk_ade_core" could be "360000000" or "180000000"; 24*4882a593Smuzhiyun The rate of "clk_codec_jpeg" could be or less than "1440000000". 25*4882a593Smuzhiyun These rate values could be configured according to performance and power 26*4882a593Smuzhiyun consumption. 27*4882a593Smuzhiyun- port: the output port. This contains one endpoint subnode, with its 28*4882a593Smuzhiyun remote-endpoint set to the phandle of the connected DSI input endpoint. 29*4882a593Smuzhiyun See Documentation/devicetree/bindings/graph.txt for more device graph info. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunOptional properties: 32*4882a593Smuzhiyun- dma-coherent: Present if dma operations are coherent. 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunA example of HiKey board hi6220 SoC specific DT entry: 36*4882a593SmuzhiyunExample: 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun ade: ade@f4100000 { 39*4882a593Smuzhiyun compatible = "hisilicon,hi6220-ade"; 40*4882a593Smuzhiyun reg = <0x0 0xf4100000 0x0 0x7800>; 41*4882a593Smuzhiyun reg-names = "ade_base"; 42*4882a593Smuzhiyun hisilicon,noc-syscon = <&medianoc_ade>; 43*4882a593Smuzhiyun resets = <&media_ctrl MEDIA_ADE>; 44*4882a593Smuzhiyun interrupts = <0 115 4>; /* ldi interrupt */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun clocks = <&media_ctrl HI6220_ADE_CORE>, 47*4882a593Smuzhiyun <&media_ctrl HI6220_CODEC_JPEG>, 48*4882a593Smuzhiyun <&media_ctrl HI6220_ADE_PIX_SRC>; 49*4882a593Smuzhiyun /*clock name*/ 50*4882a593Smuzhiyun clock-names = "clk_ade_core", 51*4882a593Smuzhiyun "clk_codec_jpeg", 52*4882a593Smuzhiyun "clk_ade_pix"; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, 55*4882a593Smuzhiyun <&media_ctrl HI6220_CODEC_JPEG>; 56*4882a593Smuzhiyun assigned-clock-rates = <360000000>, <288000000>; 57*4882a593Smuzhiyun dma-coherent; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun port { 60*4882a593Smuzhiyun ade_out: endpoint { 61*4882a593Smuzhiyun remote-endpoint = <&dsi_in>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65