Lines Matching +full:assigned +full:- +full:clock +full:- +full:rates
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <clk-uclass.h>
14 #include <dm/device-internal.h>
16 #include <dt-structs.h>
21 return (const struct clk_ops *)dev->driver->ops; in clk_dev_ops()
32 return -ENOSYS; in clk_get_by_index_platdata()
33 ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev); in clk_get_by_index_platdata()
36 clk->id = cells[0].arg[0]; in clk_get_by_index_platdata()
46 if (args->args_count > 1) { in clk_of_xlate_default()
47 debug("Invaild args_count: %d\n", args->args_count); in clk_of_xlate_default()
48 return -EINVAL; in clk_of_xlate_default()
51 if (args->args_count) in clk_of_xlate_default()
52 clk->id = args->args[0]; in clk_of_xlate_default()
54 clk->id = 0; in clk_of_xlate_default()
70 clk->dev = NULL; in clk_get_by_indexed_prop()
72 ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0, in clk_get_by_indexed_prop()
87 clk->dev = dev_clk; in clk_get_by_indexed_prop()
91 if (ops->of_xlate) in clk_get_by_indexed_prop()
92 ret = ops->of_xlate(clk, &args); in clk_get_by_indexed_prop()
112 bulk->count = 0; in clk_get_bulk()
114 count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells"); in clk_get_bulk()
118 bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL); in clk_get_bulk()
119 if (!bulk->clks) in clk_get_bulk()
120 return -ENOMEM; in clk_get_bulk()
123 ret = clk_get_by_index(dev, i, &bulk->clks[i]); in clk_get_bulk()
127 ++bulk->count; in clk_get_bulk()
133 err = clk_release_all(bulk->clks, bulk->count); in clk_get_bulk()
148 num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents", in clk_set_default_parents()
149 "#clock-cells"); in clk_set_default_parents()
151 debug("%s: could not read assigned-clock-parents for %p\n", in clk_set_default_parents()
157 ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents", in clk_set_default_parents()
160 debug("%s: could not get parent clock %d for %s\n", in clk_set_default_parents()
165 ret = clk_get_by_indexed_prop(dev, "assigned-clocks", in clk_set_default_parents()
168 debug("%s: could not get assigned clock %d for %s\n", in clk_set_default_parents()
176 * Not all drivers may support clock-reparenting (as of now). in clk_set_default_parents()
179 if (ret == -ENOSYS) in clk_set_default_parents()
183 debug("%s: failed to reparent clock %d for %s\n", in clk_set_default_parents()
199 u32 *rates = NULL; in clk_set_default_rates() local
201 size = dev_read_size(dev, "assigned-clock-rates"); in clk_set_default_rates()
206 rates = calloc(num_rates, sizeof(u32)); in clk_set_default_rates()
207 if (!rates) in clk_set_default_rates()
208 return -ENOMEM; in clk_set_default_rates()
210 ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates); in clk_set_default_rates()
215 ret = clk_get_by_indexed_prop(dev, "assigned-clocks", in clk_set_default_rates()
218 debug("%s: could not get assigned clock %d for %s\n", in clk_set_default_rates()
223 ret = clk_set_rate(&clk, rates[index]); in clk_set_default_rates()
225 debug("%s: failed to set rate on clock %d for %s\n", in clk_set_default_rates()
232 free(rates); in clk_set_default_rates()
241 /* If this is running pre-reloc state, don't take any action. */ in clk_set_defaults()
242 if (!(gd->flags & GD_FLG_RELOC)) in clk_set_defaults()
264 clk->dev = NULL; in clk_get_by_name()
266 index = dev_read_stringlist_search(dev, "clock-names", name); in clk_get_by_name()
282 /* check if clock has been previously requested */ in clk_release_all()
287 if (ret && ret != -ENOSYS) in clk_release_all()
291 if (ret && ret != -ENOSYS) in clk_release_all()
306 clk->dev = dev; in clk_request()
308 if (!ops->request) in clk_request()
311 return ops->request(clk); in clk_request()
316 const struct clk_ops *ops = clk_dev_ops(clk->dev); in clk_free()
320 if (!ops->free) in clk_free()
323 return ops->free(clk); in clk_free()
328 const struct clk_ops *ops = clk_dev_ops(clk->dev); in clk_get_rate()
332 if (!ops->get_rate) in clk_get_rate()
333 return -ENOSYS; in clk_get_rate()
335 return ops->get_rate(clk); in clk_get_rate()
340 const struct clk_ops *ops = clk_dev_ops(clk->dev); in clk_set_rate()
344 if (!ops->set_rate) in clk_set_rate()
345 return -ENOSYS; in clk_set_rate()
347 return ops->set_rate(clk, rate); in clk_set_rate()
352 const struct clk_ops *ops = clk_dev_ops(clk->dev); in clk_get_phase()
354 if (!ops->get_phase) in clk_get_phase()
355 return -ENOSYS; in clk_get_phase()
357 return ops->get_phase(clk); in clk_get_phase()
362 const struct clk_ops *ops = clk_dev_ops(clk->dev); in clk_set_phase()
364 if (!ops->set_phase) in clk_set_phase()
365 return -ENOSYS; in clk_set_phase()
367 return ops->set_phase(clk, degrees); in clk_set_phase()
372 const struct clk_ops *ops = clk_dev_ops(clk->dev); in clk_set_parent()
376 if (!ops->set_parent) in clk_set_parent()
377 return -ENOSYS; in clk_set_parent()
379 return ops->set_parent(clk, parent); in clk_set_parent()
384 const struct clk_ops *ops = clk_dev_ops(clk->dev); in clk_enable()
388 if (!ops->enable) in clk_enable()
389 return -ENOSYS; in clk_enable()
391 return ops->enable(clk); in clk_enable()
398 for (i = 0; i < bulk->count; i++) { in clk_enable_bulk()
399 ret = clk_enable(&bulk->clks[i]); in clk_enable_bulk()
400 if (ret < 0 && ret != -ENOSYS) in clk_enable_bulk()
409 const struct clk_ops *ops = clk_dev_ops(clk->dev); in clk_disable()
413 if (!ops->disable) in clk_disable()
414 return -ENOSYS; in clk_disable()
416 return ops->disable(clk); in clk_disable()
423 for (i = 0; i < bulk->count; i++) { in clk_disable_bulk()
424 ret = clk_disable(&bulk->clks[i]); in clk_disable_bulk()
425 if (ret < 0 && ret != -ENOSYS) in clk_disable_bulk()
445 printf("%s - probe failed: %d\n", dev->name, ret); in clks_probe()