1*4882a593SmuzhiyunThis binding is a work-in-progress, and are based on some experimental 2*4882a593Smuzhiyunwork by benh[1]. 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunSources of clock signal can be represented by any node in the device 5*4882a593Smuzhiyuntree. Those nodes are designated as clock providers. Clock consumer 6*4882a593Smuzhiyunnodes use a phandle and clock specifier pair to connect clock provider 7*4882a593Smuzhiyunoutputs to clock inputs. Similar to the gpio specifiers, a clock 8*4882a593Smuzhiyunspecifier is an array of zero, one or more cells identifying the clock 9*4882a593Smuzhiyunoutput on a device. The length of a clock specifier is defined by the 10*4882a593Smuzhiyunvalue of a #clock-cells property in the clock provider node. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun[1] https://patchwork.ozlabs.org/patch/31551/ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun==Clock providers== 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunRequired properties: 17*4882a593Smuzhiyun#clock-cells: Number of cells in a clock specifier; Typically 0 for nodes 18*4882a593Smuzhiyun with a single clock output and 1 for nodes with multiple 19*4882a593Smuzhiyun clock outputs. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunOptional properties: 22*4882a593Smuzhiyunclock-output-names: Recommended to be a list of strings of clock output signal 23*4882a593Smuzhiyun names indexed by the first cell in the clock specifier. 24*4882a593Smuzhiyun However, the meaning of clock-output-names is domain 25*4882a593Smuzhiyun specific to the clock provider, and is only provided to 26*4882a593Smuzhiyun encourage using the same meaning for the majority of clock 27*4882a593Smuzhiyun providers. This format may not work for clock providers 28*4882a593Smuzhiyun using a complex clock specifier format. In those cases it 29*4882a593Smuzhiyun is recommended to omit this property and create a binding 30*4882a593Smuzhiyun specific names property. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun Clock consumer nodes must never directly reference 33*4882a593Smuzhiyun the provider's clock-output-names property. 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunFor example: 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun oscillator { 38*4882a593Smuzhiyun #clock-cells = <1>; 39*4882a593Smuzhiyun clock-output-names = "ckil", "ckih"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun- this node defines a device with two clock outputs, the first named 43*4882a593Smuzhiyun "ckil" and the second named "ckih". Consumer nodes always reference 44*4882a593Smuzhiyun clocks by index. The names should reflect the clock output signal 45*4882a593Smuzhiyun names for the device. 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunclock-indices: If the identifying number for the clocks in the node 48*4882a593Smuzhiyun is not linear from zero, then this allows the mapping of 49*4882a593Smuzhiyun identifiers into the clock-output-names array. 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunFor example, if we have two clocks <&oscillator 1> and <&oscillator 3>: 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun oscillator { 54*4882a593Smuzhiyun compatible = "myclocktype"; 55*4882a593Smuzhiyun #clock-cells = <1>; 56*4882a593Smuzhiyun clock-indices = <1>, <3>; 57*4882a593Smuzhiyun clock-output-names = "clka", "clkb"; 58*4882a593Smuzhiyun } 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun This ensures we do not have any empty strings in clock-output-names 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun==Clock consumers== 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunRequired properties: 66*4882a593Smuzhiyunclocks: List of phandle and clock specifier pairs, one pair 67*4882a593Smuzhiyun for each clock input to the device. Note: if the 68*4882a593Smuzhiyun clock provider specifies '0' for #clock-cells, then 69*4882a593Smuzhiyun only the phandle portion of the pair will appear. 70*4882a593Smuzhiyun 71*4882a593SmuzhiyunOptional properties: 72*4882a593Smuzhiyunclock-names: List of clock input name strings sorted in the same 73*4882a593Smuzhiyun order as the clocks property. Consumers drivers 74*4882a593Smuzhiyun will use clock-names to match clock input names 75*4882a593Smuzhiyun with clocks specifiers. 76*4882a593Smuzhiyunclock-ranges: Empty property indicating that child nodes can inherit named 77*4882a593Smuzhiyun clocks from this node. Useful for bus nodes to provide a 78*4882a593Smuzhiyun clock to their children. 79*4882a593Smuzhiyun 80*4882a593SmuzhiyunFor example: 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun device { 83*4882a593Smuzhiyun clocks = <&osc 1>, <&ref 0>; 84*4882a593Smuzhiyun clock-names = "baud", "register"; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun 88*4882a593SmuzhiyunThis represents a device with two clock inputs, named "baud" and "register". 89*4882a593SmuzhiyunThe baud clock is connected to output 1 of the &osc device, and the register 90*4882a593Smuzhiyunclock is connected to output 0 of the &ref. 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun==Example== 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* external oscillator */ 95*4882a593Smuzhiyun osc: oscillator { 96*4882a593Smuzhiyun compatible = "fixed-clock"; 97*4882a593Smuzhiyun #clock-cells = <0>; 98*4882a593Smuzhiyun clock-frequency = <32678>; 99*4882a593Smuzhiyun clock-output-names = "osc"; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* phase-locked-loop device, generates a higher frequency clock 103*4882a593Smuzhiyun * from the external oscillator reference */ 104*4882a593Smuzhiyun pll: pll@4c000 { 105*4882a593Smuzhiyun compatible = "vendor,some-pll-interface" 106*4882a593Smuzhiyun #clock-cells = <1>; 107*4882a593Smuzhiyun clocks = <&osc 0>; 108*4882a593Smuzhiyun clock-names = "ref"; 109*4882a593Smuzhiyun reg = <0x4c000 0x1000>; 110*4882a593Smuzhiyun clock-output-names = "pll", "pll-switched"; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* UART, using the low frequency oscillator for the baud clock, 114*4882a593Smuzhiyun * and the high frequency switched PLL output for register 115*4882a593Smuzhiyun * clocking */ 116*4882a593Smuzhiyun uart@a000 { 117*4882a593Smuzhiyun compatible = "fsl,imx-uart"; 118*4882a593Smuzhiyun reg = <0xa000 0x1000>; 119*4882a593Smuzhiyun interrupts = <33>; 120*4882a593Smuzhiyun clocks = <&osc 0>, <&pll 1>; 121*4882a593Smuzhiyun clock-names = "baud", "register"; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593SmuzhiyunThis DT fragment defines three devices: an external oscillator to provide a 125*4882a593Smuzhiyunlow-frequency reference clock, a PLL device to generate a higher frequency 126*4882a593Smuzhiyunclock signal, and a UART. 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun* The oscillator is fixed-frequency, and provides one clock output, named "osc". 129*4882a593Smuzhiyun* The PLL is both a clock provider and a clock consumer. It uses the clock 130*4882a593Smuzhiyun signal generated by the external oscillator, and provides two output signals 131*4882a593Smuzhiyun ("pll" and "pll-switched"). 132*4882a593Smuzhiyun* The UART has its baud clock connected the external oscillator and its 133*4882a593Smuzhiyun register clock connected to the PLL clock (the "pll-switched" signal) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun==Assigned clock parents and rates== 136*4882a593Smuzhiyun 137*4882a593SmuzhiyunSome platforms may require initial configuration of default parent clocks 138*4882a593Smuzhiyunand clock frequencies. Such a configuration can be specified in a device tree 139*4882a593Smuzhiyunnode through assigned-clocks, assigned-clock-parents and assigned-clock-rates 140*4882a593Smuzhiyunproperties. The assigned-clock-parents property should contain a list of parent 141*4882a593Smuzhiyunclocks in the form of a phandle and clock specifier pair and the 142*4882a593Smuzhiyunassigned-clock-rates property should contain a list of frequencies in Hz. Both 143*4882a593Smuzhiyunthese properties should correspond to the clocks listed in the assigned-clocks 144*4882a593Smuzhiyunproperty. 145*4882a593Smuzhiyun 146*4882a593SmuzhiyunTo skip setting parent or rate of a clock its corresponding entry should be 147*4882a593Smuzhiyunset to 0, or can be omitted if it is not followed by any non-zero entry. 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun uart@a000 { 150*4882a593Smuzhiyun compatible = "fsl,imx-uart"; 151*4882a593Smuzhiyun reg = <0xa000 0x1000>; 152*4882a593Smuzhiyun ... 153*4882a593Smuzhiyun clocks = <&osc 0>, <&pll 1>; 154*4882a593Smuzhiyun clock-names = "baud", "register"; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun assigned-clocks = <&clkcon 0>, <&pll 2>; 157*4882a593Smuzhiyun assigned-clock-parents = <&pll 2>; 158*4882a593Smuzhiyun assigned-clock-rates = <0>, <460800>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593SmuzhiyunIn this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and 162*4882a593Smuzhiyunthe <&pll 2> clock is assigned a frequency value of 460800 Hz. 163*4882a593Smuzhiyun 164*4882a593SmuzhiyunConfiguring a clock's parent and rate through the device node that consumes 165*4882a593Smuzhiyunthe clock can be done only for clocks that have a single user. Specifying 166*4882a593Smuzhiyunconflicting parent or rate configuration in multiple consumer nodes for 167*4882a593Smuzhiyuna shared clock is forbidden. 168*4882a593Smuzhiyun 169*4882a593SmuzhiyunConfiguration of common clocks, which affect multiple consumer devices can 170*4882a593Smuzhiyunbe similarly specified in the clock provider node. 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun==Protected clocks== 173*4882a593Smuzhiyun 174*4882a593SmuzhiyunSome platforms or firmwares may not fully expose all the clocks to the OS, such 175*4882a593Smuzhiyunas in situations where those clks are used by drivers running in ARM secure 176*4882a593Smuzhiyunexecution levels. Such a configuration can be specified in device tree with the 177*4882a593Smuzhiyunprotected-clocks property in the form of a clock specifier list. This property should 178*4882a593Smuzhiyunonly be specified in the node that is providing the clocks being protected: 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun clock-controller@a000f000 { 181*4882a593Smuzhiyun compatible = "vendor,clk95; 182*4882a593Smuzhiyun reg = <0xa000f000 0x1000> 183*4882a593Smuzhiyun #clocks-cells = <1>; 184*4882a593Smuzhiyun ... 185*4882a593Smuzhiyun protected-clocks = <UART3_CLK>, <SPI5_CLK>; 186*4882a593Smuzhiyun }; 187