1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards 4*4882a593Smuzhiyun * device tree source 5*4882a593Smuzhiyun*/ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/sound/samsung-i2s.h> 8*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 9*4882a593Smuzhiyun#include <dt-bindings/clock/maxim,max77686.h> 10*4882a593Smuzhiyun#include "exynos4412.dtsi" 11*4882a593Smuzhiyun#include "exynos4412-ppmu-common.dtsi" 12*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 13*4882a593Smuzhiyun#include "exynos-mfc-reserved-memory.dtsi" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun chosen { 17*4882a593Smuzhiyun stdout-path = &serial_1; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun firmware@204f000 { 21*4882a593Smuzhiyun compatible = "samsung,secure-firmware"; 22*4882a593Smuzhiyun reg = <0x0204F000 0x1000>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun gpio_keys { 26*4882a593Smuzhiyun compatible = "gpio-keys"; 27*4882a593Smuzhiyun pinctrl-names = "default"; 28*4882a593Smuzhiyun pinctrl-0 = <&gpio_power_key>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun power_key { 31*4882a593Smuzhiyun gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; 32*4882a593Smuzhiyun linux,code = <KEY_POWER>; 33*4882a593Smuzhiyun label = "power key"; 34*4882a593Smuzhiyun debounce-interval = <10>; 35*4882a593Smuzhiyun wakeup-source; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun sound: sound { 40*4882a593Smuzhiyun compatible = "hardkernel,odroid-xu4-audio"; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun cpu { 43*4882a593Smuzhiyun sound-dai = <&i2s0 0>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun codec { 47*4882a593Smuzhiyun sound-dai = <&hdmi>, <&max98090>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun emmc_pwrseq: pwrseq { 52*4882a593Smuzhiyun pinctrl-0 = <&emmc_rstn>; 53*4882a593Smuzhiyun pinctrl-names = "default"; 54*4882a593Smuzhiyun compatible = "mmc-pwrseq-emmc"; 55*4882a593Smuzhiyun reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun fixed-rate-clocks { 59*4882a593Smuzhiyun xxti { 60*4882a593Smuzhiyun compatible = "samsung,clock-xxti"; 61*4882a593Smuzhiyun clock-frequency = <0>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun xusbxti { 65*4882a593Smuzhiyun compatible = "samsung,clock-xusbxti"; 66*4882a593Smuzhiyun clock-frequency = <24000000>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&bus_dmc { 72*4882a593Smuzhiyun devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; 73*4882a593Smuzhiyun vdd-supply = <&buck1_reg>; 74*4882a593Smuzhiyun status = "okay"; 75*4882a593Smuzhiyun}; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun&bus_acp { 78*4882a593Smuzhiyun devfreq = <&bus_dmc>; 79*4882a593Smuzhiyun status = "okay"; 80*4882a593Smuzhiyun}; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun&bus_c2c { 83*4882a593Smuzhiyun devfreq = <&bus_dmc>; 84*4882a593Smuzhiyun status = "okay"; 85*4882a593Smuzhiyun}; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun&bus_leftbus { 88*4882a593Smuzhiyun devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; 89*4882a593Smuzhiyun vdd-supply = <&buck3_reg>; 90*4882a593Smuzhiyun status = "okay"; 91*4882a593Smuzhiyun}; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun&bus_rightbus { 94*4882a593Smuzhiyun devfreq = <&bus_leftbus>; 95*4882a593Smuzhiyun status = "okay"; 96*4882a593Smuzhiyun}; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun&bus_display { 99*4882a593Smuzhiyun devfreq = <&bus_leftbus>; 100*4882a593Smuzhiyun status = "okay"; 101*4882a593Smuzhiyun}; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun&bus_fsys { 104*4882a593Smuzhiyun devfreq = <&bus_leftbus>; 105*4882a593Smuzhiyun status = "okay"; 106*4882a593Smuzhiyun}; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun&bus_peri { 109*4882a593Smuzhiyun devfreq = <&bus_leftbus>; 110*4882a593Smuzhiyun status = "okay"; 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun&bus_mfc { 114*4882a593Smuzhiyun devfreq = <&bus_leftbus>; 115*4882a593Smuzhiyun status = "okay"; 116*4882a593Smuzhiyun}; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun&camera { 119*4882a593Smuzhiyun status = "okay"; 120*4882a593Smuzhiyun pinctrl-names = "default"; 121*4882a593Smuzhiyun pinctrl-0 = <>; 122*4882a593Smuzhiyun}; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun&clock { 125*4882a593Smuzhiyun assigned-clocks = <&clock CLK_FOUT_EPLL>; 126*4882a593Smuzhiyun assigned-clock-rates = <45158401>; 127*4882a593Smuzhiyun}; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun&clock_audss { 130*4882a593Smuzhiyun assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, 131*4882a593Smuzhiyun <&clock_audss EXYNOS_MOUT_I2S>, 132*4882a593Smuzhiyun <&clock_audss EXYNOS_DOUT_SRP>, 133*4882a593Smuzhiyun <&clock_audss EXYNOS_DOUT_AUD_BUS>, 134*4882a593Smuzhiyun <&clock_audss EXYNOS_DOUT_I2S>; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun assigned-clock-parents = <&clock CLK_FOUT_EPLL>, 137*4882a593Smuzhiyun <&clock_audss EXYNOS_MOUT_AUDSS>; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun assigned-clock-rates = <0>, <0>, 140*4882a593Smuzhiyun <196608001>, 141*4882a593Smuzhiyun <(196608001 / 2)>, 142*4882a593Smuzhiyun <(196608001 / 8)>; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun&cpu0 { 146*4882a593Smuzhiyun cpu0-supply = <&buck2_reg>; 147*4882a593Smuzhiyun}; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun&cpu0_opp_table { 150*4882a593Smuzhiyun opp-1000000000 { 151*4882a593Smuzhiyun opp-suspend; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun opp-800000000 { 154*4882a593Smuzhiyun /delete-property/opp-suspend; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun}; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun&cpu_thermal { 159*4882a593Smuzhiyun cooling-maps { 160*4882a593Smuzhiyun cooling_map0: map0 { 161*4882a593Smuzhiyun /* Corresponds to 800MHz at freq_table */ 162*4882a593Smuzhiyun cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, 163*4882a593Smuzhiyun <&cpu2 7 7>, <&cpu3 7 7>; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun cooling_map1: map1 { 166*4882a593Smuzhiyun /* Corresponds to 200MHz at freq_table */ 167*4882a593Smuzhiyun cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, 168*4882a593Smuzhiyun <&cpu2 13 13>, <&cpu3 13 13>; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun}; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun&pinctrl_1 { 174*4882a593Smuzhiyun gpio_power_key: power_key { 175*4882a593Smuzhiyun samsung,pins = "gpx1-3"; 176*4882a593Smuzhiyun samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun max77686_irq: max77686-irq { 180*4882a593Smuzhiyun samsung,pins = "gpx3-2"; 181*4882a593Smuzhiyun samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; 182*4882a593Smuzhiyun samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 183*4882a593Smuzhiyun samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun hdmi_hpd: hdmi-hpd { 187*4882a593Smuzhiyun samsung,pins = "gpx3-7"; 188*4882a593Smuzhiyun samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun emmc_rstn: emmc-rstn { 192*4882a593Smuzhiyun samsung,pins = "gpk1-2"; 193*4882a593Smuzhiyun samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun}; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun&ehci { 198*4882a593Smuzhiyun status = "okay"; 199*4882a593Smuzhiyun}; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun&exynos_usbphy { 202*4882a593Smuzhiyun status = "okay"; 203*4882a593Smuzhiyun}; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun&fimc_0 { 206*4882a593Smuzhiyun status = "okay"; 207*4882a593Smuzhiyun assigned-clocks = <&clock CLK_MOUT_FIMC0>, 208*4882a593Smuzhiyun <&clock CLK_SCLK_FIMC0>; 209*4882a593Smuzhiyun assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 210*4882a593Smuzhiyun assigned-clock-rates = <0>, <176000000>; 211*4882a593Smuzhiyun}; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun&fimc_1 { 214*4882a593Smuzhiyun status = "okay"; 215*4882a593Smuzhiyun assigned-clocks = <&clock CLK_MOUT_FIMC1>, 216*4882a593Smuzhiyun <&clock CLK_SCLK_FIMC1>; 217*4882a593Smuzhiyun assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 218*4882a593Smuzhiyun assigned-clock-rates = <0>, <176000000>; 219*4882a593Smuzhiyun}; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun&fimc_2 { 222*4882a593Smuzhiyun status = "okay"; 223*4882a593Smuzhiyun assigned-clocks = <&clock CLK_MOUT_FIMC2>, 224*4882a593Smuzhiyun <&clock CLK_SCLK_FIMC2>; 225*4882a593Smuzhiyun assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 226*4882a593Smuzhiyun assigned-clock-rates = <0>, <176000000>; 227*4882a593Smuzhiyun}; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun&fimc_3 { 230*4882a593Smuzhiyun status = "okay"; 231*4882a593Smuzhiyun assigned-clocks = <&clock CLK_MOUT_FIMC3>, 232*4882a593Smuzhiyun <&clock CLK_SCLK_FIMC3>; 233*4882a593Smuzhiyun assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 234*4882a593Smuzhiyun assigned-clock-rates = <0>, <176000000>; 235*4882a593Smuzhiyun}; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun&gpu { 238*4882a593Smuzhiyun mali-supply = <&buck4_reg>; 239*4882a593Smuzhiyun status = "okay"; 240*4882a593Smuzhiyun}; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun&hdmi { 243*4882a593Smuzhiyun hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; 244*4882a593Smuzhiyun pinctrl-names = "default"; 245*4882a593Smuzhiyun pinctrl-0 = <&hdmi_hpd>; 246*4882a593Smuzhiyun vdd-supply = <&ldo8_reg>; 247*4882a593Smuzhiyun vdd_osc-supply = <&ldo10_reg>; 248*4882a593Smuzhiyun vdd_pll-supply = <&ldo8_reg>; 249*4882a593Smuzhiyun ddc = <&i2c_2>; 250*4882a593Smuzhiyun status = "okay"; 251*4882a593Smuzhiyun}; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun&hdmicec { 254*4882a593Smuzhiyun status = "okay"; 255*4882a593Smuzhiyun}; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun&hsotg { 258*4882a593Smuzhiyun dr_mode = "peripheral"; 259*4882a593Smuzhiyun status = "okay"; 260*4882a593Smuzhiyun vusb_d-supply = <&ldo15_reg>; 261*4882a593Smuzhiyun vusb_a-supply = <&ldo12_reg>; 262*4882a593Smuzhiyun}; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun&i2c_0 { 265*4882a593Smuzhiyun samsung,i2c-sda-delay = <100>; 266*4882a593Smuzhiyun samsung,i2c-max-bus-freq = <400000>; 267*4882a593Smuzhiyun status = "okay"; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun usb3503: usb3503@8 { 270*4882a593Smuzhiyun compatible = "smsc,usb3503"; 271*4882a593Smuzhiyun reg = <0x08>; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun intn-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; 274*4882a593Smuzhiyun connect-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>; 275*4882a593Smuzhiyun reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; 276*4882a593Smuzhiyun initial-mode = <1>; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun max77686: pmic@9 { 280*4882a593Smuzhiyun compatible = "maxim,max77686"; 281*4882a593Smuzhiyun interrupt-parent = <&gpx3>; 282*4882a593Smuzhiyun interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 283*4882a593Smuzhiyun pinctrl-names = "default"; 284*4882a593Smuzhiyun pinctrl-0 = <&max77686_irq>; 285*4882a593Smuzhiyun reg = <0x09>; 286*4882a593Smuzhiyun #clock-cells = <1>; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun voltage-regulators { 289*4882a593Smuzhiyun ldo1_reg: LDO1 { 290*4882a593Smuzhiyun regulator-name = "VDD_ALIVE_1.0V"; 291*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 292*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 293*4882a593Smuzhiyun regulator-always-on; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun ldo2_reg: LDO2 { 297*4882a593Smuzhiyun regulator-name = "VDDQ_M1_2_1.8V"; 298*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 299*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 300*4882a593Smuzhiyun regulator-always-on; 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun ldo3_reg: LDO3 { 304*4882a593Smuzhiyun regulator-name = "VDDQ_EXT_1.8V"; 305*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 306*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 307*4882a593Smuzhiyun regulator-always-on; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun ldo4_reg: LDO4 { 311*4882a593Smuzhiyun regulator-name = "VDDQ_MMC2_2.8V"; 312*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 313*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 314*4882a593Smuzhiyun regulator-boot-on; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun ldo5_reg: LDO5 { 318*4882a593Smuzhiyun regulator-name = "VDDQ_MMC1_3_1.8V"; 319*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 320*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 321*4882a593Smuzhiyun regulator-always-on; 322*4882a593Smuzhiyun regulator-boot-on; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun ldo6_reg: LDO6 { 326*4882a593Smuzhiyun regulator-name = "VDD10_MPLL_1.0V"; 327*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 328*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 329*4882a593Smuzhiyun regulator-always-on; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun ldo7_reg: LDO7 { 333*4882a593Smuzhiyun regulator-name = "VDD10_XPLL_1.0V"; 334*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 335*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 336*4882a593Smuzhiyun regulator-always-on; 337*4882a593Smuzhiyun }; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun ldo8_reg: LDO8 { 340*4882a593Smuzhiyun regulator-name = "VDD10_HDMI_1.0V"; 341*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 342*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun ldo10_reg: LDO10 { 346*4882a593Smuzhiyun regulator-name = "VDDQ_MIPIHSI_1.8V"; 347*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 348*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 349*4882a593Smuzhiyun }; 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun ldo11_reg: LDO11 { 352*4882a593Smuzhiyun regulator-name = "VDD18_ABB1_1.8V"; 353*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 354*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 355*4882a593Smuzhiyun regulator-always-on; 356*4882a593Smuzhiyun }; 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun ldo12_reg: LDO12 { 359*4882a593Smuzhiyun regulator-name = "VDD33_USB_3.3V"; 360*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 361*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 362*4882a593Smuzhiyun regulator-always-on; 363*4882a593Smuzhiyun regulator-boot-on; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun ldo13_reg: LDO13 { 367*4882a593Smuzhiyun regulator-name = "VDDQ_C2C_W_1.8V"; 368*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 369*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 370*4882a593Smuzhiyun regulator-always-on; 371*4882a593Smuzhiyun regulator-boot-on; 372*4882a593Smuzhiyun }; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun ldo14_reg: LDO14 { 375*4882a593Smuzhiyun regulator-name = "VDD18_ABB0_2_1.8V"; 376*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 377*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 378*4882a593Smuzhiyun regulator-always-on; 379*4882a593Smuzhiyun regulator-boot-on; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun ldo15_reg: LDO15 { 383*4882a593Smuzhiyun regulator-name = "VDD10_HSIC_1.0V"; 384*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 385*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 386*4882a593Smuzhiyun regulator-always-on; 387*4882a593Smuzhiyun regulator-boot-on; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun ldo16_reg: LDO16 { 391*4882a593Smuzhiyun regulator-name = "VDD18_HSIC_1.8V"; 392*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 393*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 394*4882a593Smuzhiyun regulator-always-on; 395*4882a593Smuzhiyun regulator-boot-on; 396*4882a593Smuzhiyun }; 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun ldo20_reg: LDO20 { 399*4882a593Smuzhiyun regulator-name = "LDO20_1.8V"; 400*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 401*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun ldo21_reg: LDO21 { 405*4882a593Smuzhiyun regulator-name = "TFLASH_2.8V"; 406*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 407*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 408*4882a593Smuzhiyun regulator-boot-on; 409*4882a593Smuzhiyun }; 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun ldo22_reg: LDO22 { 412*4882a593Smuzhiyun /* 413*4882a593Smuzhiyun * Only U3 uses it, so let it define the 414*4882a593Smuzhiyun * constraints 415*4882a593Smuzhiyun */ 416*4882a593Smuzhiyun regulator-name = "LDO22"; 417*4882a593Smuzhiyun regulator-boot-on; 418*4882a593Smuzhiyun }; 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun ldo25_reg: LDO25 { 421*4882a593Smuzhiyun regulator-name = "VDDQ_LCD_1.8V"; 422*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 423*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 424*4882a593Smuzhiyun regulator-always-on; 425*4882a593Smuzhiyun regulator-boot-on; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun buck1_reg: BUCK1 { 429*4882a593Smuzhiyun regulator-name = "VDD_MIF"; 430*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 431*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 432*4882a593Smuzhiyun regulator-always-on; 433*4882a593Smuzhiyun regulator-boot-on; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun buck2_reg: BUCK2 { 437*4882a593Smuzhiyun regulator-name = "VDD_ARM"; 438*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 439*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 440*4882a593Smuzhiyun regulator-always-on; 441*4882a593Smuzhiyun regulator-boot-on; 442*4882a593Smuzhiyun }; 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun buck3_reg: BUCK3 { 445*4882a593Smuzhiyun regulator-name = "VDD_INT"; 446*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 447*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 448*4882a593Smuzhiyun regulator-always-on; 449*4882a593Smuzhiyun regulator-boot-on; 450*4882a593Smuzhiyun }; 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun buck4_reg: BUCK4 { 453*4882a593Smuzhiyun regulator-name = "VDD_G3D"; 454*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 455*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 456*4882a593Smuzhiyun regulator-microvolt-offset = <50000>; 457*4882a593Smuzhiyun }; 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun buck5_reg: BUCK5 { 460*4882a593Smuzhiyun regulator-name = "VDDQ_CKEM1_2_1.2V"; 461*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 462*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 463*4882a593Smuzhiyun regulator-always-on; 464*4882a593Smuzhiyun regulator-boot-on; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun buck6_reg: BUCK6 { 468*4882a593Smuzhiyun regulator-name = "BUCK6_1.35V"; 469*4882a593Smuzhiyun regulator-min-microvolt = <1350000>; 470*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 471*4882a593Smuzhiyun regulator-always-on; 472*4882a593Smuzhiyun regulator-boot-on; 473*4882a593Smuzhiyun }; 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun buck7_reg: BUCK7 { 476*4882a593Smuzhiyun regulator-name = "BUCK7_2.0V"; 477*4882a593Smuzhiyun regulator-min-microvolt = <2000000>; 478*4882a593Smuzhiyun regulator-max-microvolt = <2000000>; 479*4882a593Smuzhiyun regulator-always-on; 480*4882a593Smuzhiyun }; 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun buck8_reg: BUCK8 { 483*4882a593Smuzhiyun /* 484*4882a593Smuzhiyun * Constraints set by specific board: X, 485*4882a593Smuzhiyun * X2 and U3. 486*4882a593Smuzhiyun */ 487*4882a593Smuzhiyun regulator-name = "BUCK8_2.8V"; 488*4882a593Smuzhiyun }; 489*4882a593Smuzhiyun }; 490*4882a593Smuzhiyun }; 491*4882a593Smuzhiyun}; 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun&i2c_1 { 494*4882a593Smuzhiyun status = "okay"; 495*4882a593Smuzhiyun max98090: max98090@10 { 496*4882a593Smuzhiyun compatible = "maxim,max98090"; 497*4882a593Smuzhiyun reg = <0x10>; 498*4882a593Smuzhiyun interrupt-parent = <&gpx0>; 499*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_NONE>; 500*4882a593Smuzhiyun clocks = <&i2s0 CLK_I2S_CDCLK>; 501*4882a593Smuzhiyun clock-names = "mclk"; 502*4882a593Smuzhiyun #sound-dai-cells = <0>; 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun}; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun&i2c_2 { 507*4882a593Smuzhiyun status = "okay"; 508*4882a593Smuzhiyun}; 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun&i2c_8 { 511*4882a593Smuzhiyun status = "okay"; 512*4882a593Smuzhiyun}; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun&i2s0 { 515*4882a593Smuzhiyun pinctrl-0 = <&i2s0_bus>; 516*4882a593Smuzhiyun pinctrl-names = "default"; 517*4882a593Smuzhiyun status = "okay"; 518*4882a593Smuzhiyun assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; 519*4882a593Smuzhiyun assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; 520*4882a593Smuzhiyun}; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun&mixer { 523*4882a593Smuzhiyun status = "okay"; 524*4882a593Smuzhiyun}; 525*4882a593Smuzhiyun 526*4882a593Smuzhiyun&mshc_0 { 527*4882a593Smuzhiyun pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; 528*4882a593Smuzhiyun pinctrl-names = "default"; 529*4882a593Smuzhiyun vmmc-supply = <&ldo20_reg>; 530*4882a593Smuzhiyun mmc-pwrseq = <&emmc_pwrseq>; 531*4882a593Smuzhiyun status = "okay"; 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun broken-cd; 534*4882a593Smuzhiyun card-detect-delay = <200>; 535*4882a593Smuzhiyun samsung,dw-mshc-ciu-div = <3>; 536*4882a593Smuzhiyun samsung,dw-mshc-sdr-timing = <2 3>; 537*4882a593Smuzhiyun samsung,dw-mshc-ddr-timing = <1 2>; 538*4882a593Smuzhiyun bus-width = <8>; 539*4882a593Smuzhiyun cap-mmc-highspeed; 540*4882a593Smuzhiyun}; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun&rtc { 543*4882a593Smuzhiyun status = "okay"; 544*4882a593Smuzhiyun clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; 545*4882a593Smuzhiyun clock-names = "rtc", "rtc_src"; 546*4882a593Smuzhiyun}; 547*4882a593Smuzhiyun 548*4882a593Smuzhiyun&sdhci_2 { 549*4882a593Smuzhiyun bus-width = <4>; 550*4882a593Smuzhiyun pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 551*4882a593Smuzhiyun pinctrl-names = "default"; 552*4882a593Smuzhiyun vmmc-supply = <&ldo21_reg>; 553*4882a593Smuzhiyun vqmmc-supply = <&ldo4_reg>; 554*4882a593Smuzhiyun cd-gpios = <&gpk2 2 GPIO_ACTIVE_LOW>; 555*4882a593Smuzhiyun status = "okay"; 556*4882a593Smuzhiyun}; 557*4882a593Smuzhiyun 558*4882a593Smuzhiyun&serial_0 { 559*4882a593Smuzhiyun status = "okay"; 560*4882a593Smuzhiyun}; 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun&serial_1 { 563*4882a593Smuzhiyun status = "okay"; 564*4882a593Smuzhiyun}; 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun&tmu { 567*4882a593Smuzhiyun vtmu-supply = <&ldo10_reg>; 568*4882a593Smuzhiyun status = "okay"; 569*4882a593Smuzhiyun}; 570