1*4882a593Smuzhiyun* Qualcomm AHCI SATA Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunSATA nodes are defined to describe on-chip Serial ATA controllers. 4*4882a593SmuzhiyunEach SATA controller should have its own node. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible : compatible list, must contain "generic-ahci" 8*4882a593Smuzhiyun- interrupts : <interrupt mapping for SATA IRQ> 9*4882a593Smuzhiyun- reg : <registers mapping> 10*4882a593Smuzhiyun- phys : Must contain exactly one entry as specified 11*4882a593Smuzhiyun in phy-bindings.txt 12*4882a593Smuzhiyun- phy-names : Must be "sata-phy" 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRequired properties for "qcom,ipq806x-ahci" compatible: 15*4882a593Smuzhiyun- clocks : Must contain an entry for each entry in clock-names. 16*4882a593Smuzhiyun- clock-names : Shall be: 17*4882a593Smuzhiyun "slave_iface" - Fabric port AHB clock for SATA 18*4882a593Smuzhiyun "iface" - AHB clock 19*4882a593Smuzhiyun "core" - core clock 20*4882a593Smuzhiyun "rxoob" - RX out-of-band clock 21*4882a593Smuzhiyun "pmalive" - Power Module Alive clock 22*4882a593Smuzhiyun- assigned-clocks : Shall be: 23*4882a593Smuzhiyun SATA_RXOOB_CLK 24*4882a593Smuzhiyun SATA_PMALIVE_CLK 25*4882a593Smuzhiyun- assigned-clock-rates : Shall be: 26*4882a593Smuzhiyun 100Mhz (100000000) for SATA_RXOOB_CLK 27*4882a593Smuzhiyun 100Mhz (100000000) for SATA_PMALIVE_CLK 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExample: 30*4882a593Smuzhiyun sata@29000000 { 31*4882a593Smuzhiyun compatible = "qcom,ipq806x-ahci", "generic-ahci"; 32*4882a593Smuzhiyun reg = <0x29000000 0x180>; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun interrupts = <0 209 0x0>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clocks = <&gcc SFAB_SATA_S_H_CLK>, 37*4882a593Smuzhiyun <&gcc SATA_H_CLK>, 38*4882a593Smuzhiyun <&gcc SATA_A_CLK>, 39*4882a593Smuzhiyun <&gcc SATA_RXOOB_CLK>, 40*4882a593Smuzhiyun <&gcc SATA_PMALIVE_CLK>; 41*4882a593Smuzhiyun clock-names = "slave_iface", "iface", "core", 42*4882a593Smuzhiyun "rxoob", "pmalive"; 43*4882a593Smuzhiyun assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; 44*4882a593Smuzhiyun assigned-clock-rates = <100000000>, <100000000>; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun phys = <&sata_phy>; 47*4882a593Smuzhiyun phy-names = "sata-phy"; 48*4882a593Smuzhiyun }; 49