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/OK3568_Linux_fs/kernel/drivers/amba/
H A Dtegra-ahb.c21 #include <soc/tegra/ahb.h>
23 #define DRV_NAME "tegra-ahb"
79 * 0x4 for the AHB IP block. According to the TRM, the low byte
126 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset) in gizmo_readl() argument
128 return readl(ahb->regs + offset); in gizmo_readl()
131 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset) in gizmo_writel() argument
133 writel(value, ahb->regs + offset); in gizmo_writel()
141 struct tegra_ahb *ahb; in tegra_ahb_enable_smmu() local
146 ahb = dev_get_drvdata(dev); in tegra_ahb_enable_smmu()
147 val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL); in tegra_ahb_enable_smmu()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-imx35.c34 unsigned char arm, ahb, sel; member
38 { .arm = 1, .ahb = 4, .sel = 0},
39 { .arm = 1, .ahb = 3, .sel = 1},
40 { .arm = 2, .ahb = 2, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
43 { .arm = 0, .ahb = 0, .sel = 0},
44 { .arm = 4, .ahb = 1, .sel = 0},
45 { .arm = 1, .ahb = 5, .sel = 0},
46 { .arm = 1, .ahb = 8, .sel = 0},
[all …]
H A Dclk-imx27.c41 "ahb", "ipg", "per1_div", "per2_div",
70 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); in _mx27_clocks_init()
71 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx27_clocks_init()
73 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); in _mx27_clocks_init()
74 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); in _mx27_clocks_init()
77 clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); in _mx27_clocks_init()
78 clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); in _mx27_clocks_init()
140 clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); in _mx27_clocks_init()
141 clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); in _mx27_clocks_init()
142 clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); in _mx27_clocks_init()
[all …]
H A Dclk-imx25.c46 static const char *per_sel_clks[] = { "ahb", "upll", };
47 static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
53 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
86 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
88 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
140 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); in __mx25_clocks_init()
142 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); in __mx25_clocks_init()
143 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); in __mx25_clocks_init()
144 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); in __mx25_clocks_init()
145 clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21); in __mx25_clocks_init()
[all …]
H A Dclk-imx31.c40 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
74 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); in _mx31_clocks_init()
75 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); in _mx31_clocks_init()
76 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); in _mx31_clocks_init()
93 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); in _mx31_clocks_init()
111 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); in _mx31_clocks_init()
122 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); in _mx31_clocks_init()
123 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); in _mx31_clocks_init()
H A Dclk-imx6ul.c64 "dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
291 hws[IMX6UL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2); in imx6ul_clocks_init()
330 …hws[IMX6UL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0… in imx6ul_clocks_init()
333 …hws[IMX6UL_CLK_AIPSTZ1] = imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICA… in imx6ul_clocks_init()
334 …hws[IMX6UL_CLK_AIPSTZ2] = imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICA… in imx6ul_clocks_init()
336 …hws[IMX6UL_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count… in imx6ul_clocks_init()
337 …hws[IMX6UL_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count… in imx6ul_clocks_init()
339 hws[IMX6UL_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem", "ahb", base + 0x68, 8); in imx6ul_clocks_init()
340 hws[IMX6UL_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk", "ahb", base + 0x68, 10); in imx6ul_clocks_init()
343 hws[IMX6ULL_CLK_DCP_CLK] = imx_clk_hw_gate2("dcp", "ahb", base + 0x68, 10); in imx6ul_clocks_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu-sun4i-a10.c244 .hw.init = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
265 .hw.init = CLK_HW_INIT_PARENTS("ahb",
279 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
290 static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",
293 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
295 static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",
297 static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",
299 static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",
301 static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",
303 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
[all …]
H A Dccu-sun5i.c214 .hw.init = CLK_HW_INIT_PARENTS("ahb",
228 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
241 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
243 static SUNXI_CCU_GATE(ahb_ehci_clk, "ahb-ehci", "ahb",
245 static SUNXI_CCU_GATE(ahb_ohci_clk, "ahb-ohci", "ahb",
247 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
249 static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
251 static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
253 static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
255 static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
[all …]
H A Dccu-suniv-f1c100s.c131 .hw.init = CLK_HW_INIT_PARENTS("ahb",
145 static SUNXI_CCU_DIV_TABLE(apb_clk, "apb", "ahb",
148 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb",
150 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb",
152 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb",
154 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb",
156 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb",
158 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb",
160 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb",
163 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb",
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra20-ahb.txt1 NVIDIA Tegra AHB
4 - compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
5 Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
6 '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
14 ahb: ahb@6000c004 {
15 compatible = "nvidia,tegra20-ahb";
16 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
/OK3568_Linux_fs/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun4i.c122 int axi, ahb, apb0; in clock_set_pll1() local
136 ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ in clock_set_pll1()
139 printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); in clock_set_pll1()
143 if (ahb > 4) in clock_set_pll1()
144 ahb = 3; in clock_set_pll1()
145 else if (ahb > 2) in clock_set_pll1()
146 ahb = 2; in clock_set_pll1()
147 else if (ahb > 1) in clock_set_pll1()
148 ahb = 1; in clock_set_pll1()
150 ahb = 0; in clock_set_pll1()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-gemini.c93 { 2, "gmac0-gate", "ahb", 0 },
94 { 3, "gmac1-gate", "ahb", 0 },
95 { 4, "sata0-gate", "ahb", 0 },
96 { 5, "sata1-gate", "ahb", 0 },
97 { 6, "usb0-gate", "ahb", 0 },
98 { 7, "usb1-gate", "ahb", 0 },
99 { 8, "ide-gate", "ahb", 0 },
100 { 9, "pci-gate", "ahb", 0 },
105 { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
110 { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sprd/
H A Dsc9860-clk.c524 static SPRD_COMP_CLK(sp_ahb, "sp-ahb", sp_ahb_parents, 0x2d0,
1339 static SPRD_MUX_CLK(ahb_vsp, "ahb-vsp", ahb_parents, 0x20,
1385 static SPRD_SC_GATE_CLK(vsp_dec_eb, "vsp-dec-eb", "ahb-vsp", 0x0,
1387 static SPRD_SC_GATE_CLK(vsp_ckg_eb, "vsp-ckg-eb", "ahb-vsp", 0x0,
1389 static SPRD_SC_GATE_CLK(vsp_mmu_eb, "vsp-mmu-eb", "ahb-vsp", 0x0,
1391 static SPRD_SC_GATE_CLK(vsp_enc_eb, "vsp-enc-eb", "ahb-vsp", 0x0,
1393 static SPRD_SC_GATE_CLK(vpp_eb, "vpp-eb", "ahb-vsp", 0x0,
1395 static SPRD_SC_GATE_CLK(vsp_26m_eb, "vsp-26m-eb", "ahb-vsp", 0x0,
1397 static SPRD_GATE_CLK(vsp_axi_gate, "vsp-axi-gate", "ahb-vsp", 0x8,
1399 static SPRD_GATE_CLK(vsp_enc_gate, "vsp-enc-gate", "ahb-vsp", 0x8,
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie.txt86 - "iface" Configuration AHB clock
121 - "ahb" AHB clock
128 - "iface" AHB clock
156 - "ahb" AHB reset
181 - "ahb" AHB reset
182 - "phy_ahb" PHY AHB reset
194 - "ahb" AHB Reset
206 - "ahb" AHB reset
294 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
7 title: Allwinner A10 AHB Clock Device Tree Bindings
21 - allwinner,sun4i-a10-ahb-clk
51 const: allwinner,sun4i-a10-ahb-clk
82 ahb@1c20054 {
84 compatible = "allwinner,sun4i-a10-ahb-clk";
87 clock-output-names = "ahb";
H A Dallwinner,sun5i-a13-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml#
7 title: Allwinner A13 AHB Clock Device Tree Bindings
20 const: allwinner,sun5i-a13-ahb-clk
44 ahb@1c20054 {
46 compatible = "allwinner,sun5i-a13-ahb-clk";
49 clock-output-names = "ahb";
H A Dnspire-clock.txt5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
H A Dallwinner,sun9i-a80-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-ahb-clk.yaml#
7 title: Allwinner A80 AHB Clock Device Tree Bindings
20 const: allwinner,sun9i-a80-ahb-clk
46 compatible = "allwinner,sun9i-a80-ahb-clk";
H A Dallwinner,sun4i-a10-gates-clk.yaml26 - const: allwinner,sun4i-a10-ahb-gates-clk
27 - const: allwinner,sun5i-a10s-ahb-gates-clk
28 - const: allwinner,sun5i-a13-ahb-gates-clk
29 - const: allwinner,sun7i-a20-ahb-gates-clk
100 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
102 clocks = <&ahb>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/
H A Darm-pl08x.txt15 - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
16 - lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
17 - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
18 - mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
21 which AHB master that is used.
33 - dmas: List of DMA controller phandle, request channel and AHB master id
/OK3568_Linux_fs/u-boot/arch/nds32/include/asm/arch-ag101/
H A Dag101.h14 /* AHB Controller */
22 /* AHB-to-APB Bridge */
36 /* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
40 /* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
42 /* External AHB slave1 (LCD) */
44 /* External AHB slave2 (FUSBH200) */
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/misc/
H A Dintel,ixp4xx-ahb-queue-manager.yaml5 $id: "http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#"
8 title: Intel IXP4xx AHB Queue Manager
14 The IXP4xx AHB Queue Manager maintains queues as circular buffers in
26 - const: intel,ixp4xx-ahb-queue-manager
48 compatible = "intel,ixp4xx-ahb-queue-manager";
/OK3568_Linux_fs/kernel/drivers/dma/dw/
H A DKconfig12 tristate "Synopsys DesignWare AHB DMA platform driver"
16 Support the Synopsys DesignWare AHB DMA controller. This
20 tristate "Synopsys DesignWare AHB DMA PCI driver"
25 Support the Synopsys DesignWare AHB DMA controller on the
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iommu/
H A Dnvidia,tegra30-smmu.txt10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
20 nvidia,ahb = <&ahb>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,geni-se.yaml32 - const: m-ahb
33 - const: s-ahb
37 - description: Master AHB Clock
38 - description: Slave AHB Clock
190 clock-names = "m-ahb", "s-ahb";

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