1*4882a593SmuzhiyunNVIDIA Tegra AHB 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For 5*4882a593Smuzhiyun Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain 6*4882a593Smuzhiyun '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124, 7*4882a593Smuzhiyun tegra132, or tegra210. 8*4882a593Smuzhiyun- reg : Should contain 1 register ranges(address and length). For 9*4882a593Smuzhiyun Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004 10*4882a593Smuzhiyun 0x10c>. For Tegra124, Tegra132 and Tegra210 chips, the value should 11*4882a593Smuzhiyun be be <0x6000c000 0x150>. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunExample (for a Tegra20 chip): 14*4882a593Smuzhiyun ahb: ahb@6000c004 { 15*4882a593Smuzhiyun compatible = "nvidia,tegra20-ahb"; 16*4882a593Smuzhiyun reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ 17*4882a593Smuzhiyun }; 18