1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A10 AHB Clock Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundeprecated: true 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun "#clock-cells": 17*4882a593Smuzhiyun const: 0 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun compatible: 20*4882a593Smuzhiyun enum: 21*4882a593Smuzhiyun - allwinner,sun4i-a10-ahb-clk 22*4882a593Smuzhiyun - allwinner,sun6i-a31-ahb1-clk 23*4882a593Smuzhiyun - allwinner,sun8i-h3-ahb2-clk 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun reg: 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun clocks: 29*4882a593Smuzhiyun minItems: 1 30*4882a593Smuzhiyun maxItems: 4 31*4882a593Smuzhiyun description: > 32*4882a593Smuzhiyun The parent order must match the hardware programming order. 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun clock-output-names: 35*4882a593Smuzhiyun maxItems: 1 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunrequired: 38*4882a593Smuzhiyun - "#clock-cells" 39*4882a593Smuzhiyun - compatible 40*4882a593Smuzhiyun - reg 41*4882a593Smuzhiyun - clocks 42*4882a593Smuzhiyun - clock-output-names 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunadditionalProperties: false 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunallOf: 47*4882a593Smuzhiyun - if: 48*4882a593Smuzhiyun properties: 49*4882a593Smuzhiyun compatible: 50*4882a593Smuzhiyun contains: 51*4882a593Smuzhiyun const: allwinner,sun4i-a10-ahb-clk 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun then: 54*4882a593Smuzhiyun properties: 55*4882a593Smuzhiyun clocks: 56*4882a593Smuzhiyun maxItems: 1 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun - if: 59*4882a593Smuzhiyun properties: 60*4882a593Smuzhiyun compatible: 61*4882a593Smuzhiyun contains: 62*4882a593Smuzhiyun const: allwinner,sun6i-a31-ahb1-clk 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun then: 65*4882a593Smuzhiyun properties: 66*4882a593Smuzhiyun clocks: 67*4882a593Smuzhiyun maxItems: 4 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun - if: 70*4882a593Smuzhiyun properties: 71*4882a593Smuzhiyun compatible: 72*4882a593Smuzhiyun contains: 73*4882a593Smuzhiyun const: allwinner,sun8i-h3-ahb2-clk 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun then: 76*4882a593Smuzhiyun properties: 77*4882a593Smuzhiyun clocks: 78*4882a593Smuzhiyun maxItems: 2 79*4882a593Smuzhiyun 80*4882a593Smuzhiyunexamples: 81*4882a593Smuzhiyun - | 82*4882a593Smuzhiyun ahb@1c20054 { 83*4882a593Smuzhiyun #clock-cells = <0>; 84*4882a593Smuzhiyun compatible = "allwinner,sun4i-a10-ahb-clk"; 85*4882a593Smuzhiyun reg = <0x01c20054 0x4>; 86*4882a593Smuzhiyun clocks = <&axi>; 87*4882a593Smuzhiyun clock-output-names = "ahb"; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun - | 91*4882a593Smuzhiyun ahb1@1c20054 { 92*4882a593Smuzhiyun #clock-cells = <0>; 93*4882a593Smuzhiyun compatible = "allwinner,sun6i-a31-ahb1-clk"; 94*4882a593Smuzhiyun reg = <0x01c20054 0x4>; 95*4882a593Smuzhiyun clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; 96*4882a593Smuzhiyun clock-output-names = "ahb1"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun - | 100*4882a593Smuzhiyun ahb2_clk@1c2005c { 101*4882a593Smuzhiyun #clock-cells = <0>; 102*4882a593Smuzhiyun compatible = "allwinner,sun8i-h3-ahb2-clk"; 103*4882a593Smuzhiyun reg = <0x01c2005c 0x4>; 104*4882a593Smuzhiyun clocks = <&ahb1>, <&pll6d2>; 105*4882a593Smuzhiyun clock-output-names = "ahb2"; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun... 109