1*4882a593SmuzhiyunNVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : "nvidia,tegra30-smmu" 5*4882a593Smuzhiyun- reg : Should contain 3 register banks(address and length) for each 6*4882a593Smuzhiyun of the SMMU register blocks. 7*4882a593Smuzhiyun- interrupts : Should contain MC General interrupt. 8*4882a593Smuzhiyun- nvidia,#asids : # of ASIDs 9*4882a593Smuzhiyun- dma-window : IOVA start address and length. 10*4882a593Smuzhiyun- nvidia,ahb : phandle to the ahb bus connected to SMMU. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunExample: 13*4882a593Smuzhiyun smmu { 14*4882a593Smuzhiyun compatible = "nvidia,tegra30-smmu"; 15*4882a593Smuzhiyun reg = <0x7000f010 0x02c 16*4882a593Smuzhiyun 0x7000f1f0 0x010 17*4882a593Smuzhiyun 0x7000f228 0x05c>; 18*4882a593Smuzhiyun nvidia,#asids = <4>; /* # of ASIDs */ 19*4882a593Smuzhiyun dma-window = <0 0x40000000>; /* IOVA start & length */ 20*4882a593Smuzhiyun nvidia,ahb = <&ahb>; 21*4882a593Smuzhiyun }; 22