1*4882a593Smuzhiyun* ARM PrimeCells PL080 and PL081 and derivatives DMA controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "arm,pl080", "arm,primecell"; 5*4882a593Smuzhiyun "arm,pl081", "arm,primecell"; 6*4882a593Smuzhiyun "faraday,ftdmac020", "arm,primecell" 7*4882a593Smuzhiyun- arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded 8*4882a593Smuzhiyun in the hardware and must be specified here as <0x0003b080>. This number 9*4882a593Smuzhiyun follows the PrimeCell standard numbering using the JEP106 vendor code 0x38 10*4882a593Smuzhiyun for Faraday Technology. 11*4882a593Smuzhiyun- reg: Address range of the PL08x registers 12*4882a593Smuzhiyun- interrupt: The PL08x interrupt number 13*4882a593Smuzhiyun- clocks: The clock running the IP core clock 14*4882a593Smuzhiyun- clock-names: Must contain "apb_pclk" 15*4882a593Smuzhiyun- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs 16*4882a593Smuzhiyun- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs 17*4882a593Smuzhiyun- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents 18*4882a593Smuzhiyun- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents 19*4882a593Smuzhiyun- #dma-cells: must be <2>. First cell should contain the DMA request, 20*4882a593Smuzhiyun second cell should contain either 1 or 2 depending on 21*4882a593Smuzhiyun which AHB master that is used. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunOptional properties: 24*4882a593Smuzhiyun- dma-channels: contains the total number of DMA channels supported by the DMAC 25*4882a593Smuzhiyun- dma-requests: contains the total number of DMA requests supported by the DMAC 26*4882a593Smuzhiyun- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32 27*4882a593Smuzhiyun 64, 128 or 256 bytes are legal values 28*4882a593Smuzhiyun- memcpy-bus-width: the bus width used for memcpy in bits: 8, 16 or 32 are legal 29*4882a593Smuzhiyun values, the Faraday FTDMAC020 can also accept 64 bits 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunClients 32*4882a593SmuzhiyunRequired properties: 33*4882a593Smuzhiyun- dmas: List of DMA controller phandle, request channel and AHB master id 34*4882a593Smuzhiyun- dma-names: Names of the aforementioned requested channels 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunExample: 37*4882a593Smuzhiyun 38*4882a593Smuzhiyundmac0: dma-controller@10130000 { 39*4882a593Smuzhiyun compatible = "arm,pl080", "arm,primecell"; 40*4882a593Smuzhiyun reg = <0x10130000 0x1000>; 41*4882a593Smuzhiyun interrupt-parent = <&vica>; 42*4882a593Smuzhiyun interrupts = <15>; 43*4882a593Smuzhiyun clocks = <&hclkdma0>; 44*4882a593Smuzhiyun clock-names = "apb_pclk"; 45*4882a593Smuzhiyun lli-bus-interface-ahb1; 46*4882a593Smuzhiyun lli-bus-interface-ahb2; 47*4882a593Smuzhiyun mem-bus-interface-ahb2; 48*4882a593Smuzhiyun memcpy-burst-size = <256>; 49*4882a593Smuzhiyun memcpy-bus-width = <32>; 50*4882a593Smuzhiyun #dma-cells = <2>; 51*4882a593Smuzhiyun}; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyundevice@40008000 { 54*4882a593Smuzhiyun ... 55*4882a593Smuzhiyun dmas = <&dmac0 0 2 56*4882a593Smuzhiyun &dmac0 1 2>; 57*4882a593Smuzhiyun dma-names = "tx", "rx"; 58*4882a593Smuzhiyun ... 59*4882a593Smuzhiyun}; 60