1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 Andes Technology Corporation 3*4882a593Smuzhiyun * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4*4882a593Smuzhiyun * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __AG101_H 10*4882a593Smuzhiyun #define __AG101_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Hardware register bases */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* AHB Controller */ 15*4882a593Smuzhiyun #define CONFIG_FTAHBC020S_BASE 0x90100000 16*4882a593Smuzhiyun /* Static Memory Controller (SRAM) */ 17*4882a593Smuzhiyun #define CONFIG_FTSMC020_BASE 0x90200000 18*4882a593Smuzhiyun /* FTSDMC021 SDRAM Controller */ 19*4882a593Smuzhiyun #define CONFIG_FTSDMC021_BASE 0x90300000 20*4882a593Smuzhiyun /* DMA Controller */ 21*4882a593Smuzhiyun #define CONFIG_FTDMAC020_BASE 0x90400000 22*4882a593Smuzhiyun /* AHB-to-APB Bridge */ 23*4882a593Smuzhiyun #define CONFIG_FTAPBBRG020S_01_BASE 0x90500000 24*4882a593Smuzhiyun /* LCD Controller */ 25*4882a593Smuzhiyun #define CONFIG_FTLCDC100_BASE 0x90600000 26*4882a593Smuzhiyun /* Reserved */ 27*4882a593Smuzhiyun #define CONFIG_RESERVED_01_BASE 0x90700000 28*4882a593Smuzhiyun /* Reserved */ 29*4882a593Smuzhiyun #define CONFIG_RESERVED_02_BASE 0x90800000 30*4882a593Smuzhiyun /* Ethernet */ 31*4882a593Smuzhiyun #define CONFIG_FTMAC100_BASE 0x90900000 32*4882a593Smuzhiyun /* External USB host */ 33*4882a593Smuzhiyun #define CONFIG_EXT_USB_HOST_BASE 0x90A00000 34*4882a593Smuzhiyun /* USB Device */ 35*4882a593Smuzhiyun #define CONFIG_USB_DEV_BASE 0x90B00000 36*4882a593Smuzhiyun /* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */ 37*4882a593Smuzhiyun #define CONFIG_EXT_AHBPCIBRG_BASE 0x90C00000 38*4882a593Smuzhiyun /* Reserved */ 39*4882a593Smuzhiyun #define CONFIG_RESERVED_03_BASE 0x90D00000 40*4882a593Smuzhiyun /* External AHB-to-APB Bridger (FTAPBBRG020S_02) */ 41*4882a593Smuzhiyun #define CONFIG_EXT_AHBAPBBRG_BASE 0x90E00000 42*4882a593Smuzhiyun /* External AHB slave1 (LCD) */ 43*4882a593Smuzhiyun #define CONFIG_EXT_AHBSLAVE01_BASE 0x90F00000 44*4882a593Smuzhiyun /* External AHB slave2 (FUSBH200) */ 45*4882a593Smuzhiyun #define CONFIG_EXT_AHBSLAVE02_BASE 0x92000000 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* DEBUG LED */ 48*4882a593Smuzhiyun #define CONFIG_DEBUG_LED 0x902FFFFC 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* APB Device definitions */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Power Management Unit */ 53*4882a593Smuzhiyun #define CONFIG_FTPMU010_BASE 0x98100000 54*4882a593Smuzhiyun /* BT UART 2/IrDA (UART 01 in Linux) */ 55*4882a593Smuzhiyun #define CONFIG_FTUART010_01_BASE 0x98300000 56*4882a593Smuzhiyun /* Counter/Timers */ 57*4882a593Smuzhiyun #define CONFIG_FTTMR010_BASE 0x98400000 58*4882a593Smuzhiyun /* Watchdog Timer */ 59*4882a593Smuzhiyun #define CONFIG_FTWDT010_BASE 0x98500000 60*4882a593Smuzhiyun /* Real Time Clock */ 61*4882a593Smuzhiyun #define CONFIG_FTRTC010_BASE 0x98600000 62*4882a593Smuzhiyun /* GPIO */ 63*4882a593Smuzhiyun #define CONFIG_FTGPIO010_BASE 0x98700000 64*4882a593Smuzhiyun /* Interrupt Controller */ 65*4882a593Smuzhiyun #define CONFIG_FTINTC010_BASE 0x98800000 66*4882a593Smuzhiyun /* I2C */ 67*4882a593Smuzhiyun #define CONFIG_FTIIC010_BASE 0x98A00000 68*4882a593Smuzhiyun /* Reserved */ 69*4882a593Smuzhiyun #define CONFIG_RESERVED_04_BASE 0x98C00000 70*4882a593Smuzhiyun /* Compat Flash Controller */ 71*4882a593Smuzhiyun #define CONFIG_FTCFC010_BASE 0x98D00000 72*4882a593Smuzhiyun /* SD Controller */ 73*4882a593Smuzhiyun #define CONFIG_FTSDC010_BASE 0x98E00000 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Synchronous Serial Port Controller (SSP) I2S/AC97 */ 76*4882a593Smuzhiyun #define CONFIG_FTSSP010_02_BASE 0x99400000 77*4882a593Smuzhiyun /* ST UART ? SSP 02 (UART 02 in Linux) */ 78*4882a593Smuzhiyun #define CONFIG_FTUART010_02_BASE 0x99600000 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* The following address was not defined in Linux */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* FF UART 3 */ 83*4882a593Smuzhiyun #define CONFIG_FTUART010_03_BASE 0x98200000 84*4882a593Smuzhiyun /* Synchronous Serial Port Controller (SSP) 01 */ 85*4882a593Smuzhiyun #define CONFIG_FTSSP010_01_BASE 0x98B00000 86*4882a593Smuzhiyun /* IrDA */ 87*4882a593Smuzhiyun #define CONFIG_IRDA_BASE 0x98900000 88*4882a593Smuzhiyun /* PWM - Pulse Width Modulator Controller */ 89*4882a593Smuzhiyun #define CONFIG_PMW_BASE 0x99100000 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif /* __AG101_H */ 92