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/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Drs780_dpm.c571 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_before_set_eng_clock()
578 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
588 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_after_set_eng_clock()
595 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
728 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rs780_parse_pplib_non_clock_info()
731 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
736 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
737 rps->vclk = RS780_DEFAULT_VCLK_FREQ; in rs780_parse_pplib_non_clock_info()
946 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
995 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
H A Dradeon_uvd.c943 * @vclk: wanted VCLK
953 * @optimal_vclk_div: resulting vclk post divider
960 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
975 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
989 /* calc vclk divider with current vco freq */ in radeon_uvd_calc_upll_dividers()
990 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
1002 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
H A Dsumo_dpm.c824 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
840 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_before_set_eng_clock()
858 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_after_set_eng_clock()
1414 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in sumo_parse_pplib_non_clock_info()
1417 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1802 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1825 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1833 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
H A Dtrinity_dpm.c898 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
910 if ((rps1->vclk == rps2->vclk) && in trinity_uvd_clocks_equal()
943 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
954 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1458 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && in trinity_get_uvd_clock_index()
1692 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in trinity_parse_pplib_non_clock_info()
1695 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1933 pi->sys_info.uvd_clock_table_entries[i].vclk = in trinity_parse_sys_info_table()
2019 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
2044 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
H A Drv6xx_dpm.c1518 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_before_set_eng_clock()
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1535 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_after_set_eng_clock()
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1803 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1806 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
H A Drv770_dpm.c1438 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_before_set_eng_clock()
1445 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1455 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_after_set_eng_clock()
1462 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2153 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rv7xx_parse_pplib_non_clock_info()
2156 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2161 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2162 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2440 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2484 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
H A Dradeon_asic.h411 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
478 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
535 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
536 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
749 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
787 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
/OK3568_Linux_fs/kernel/drivers/video/fbdev/nvidia/
H A Dnv_hw.c380 static void nv4UpdateArbitrationSettings(unsigned VClk, in nv4UpdateArbitrationSettings() argument
402 sim_data.pclk_khz = VClk; in nv4UpdateArbitrationSettings()
618 static void nv10UpdateArbitrationSettings(unsigned VClk, in nv10UpdateArbitrationSettings() argument
642 sim_data.pclk_khz = VClk; in nv10UpdateArbitrationSettings()
676 static void nForceUpdateArbitrationSettings(unsigned VClk, in nForceUpdateArbitrationSettings() argument
744 sim_data.pclk_khz = VClk; in nForceUpdateArbitrationSettings()
771 unsigned VClk, Freq; in CalcVClock() local
776 VClk = (unsigned)clockIn; in CalcVClock()
787 Freq = VClk << P; in CalcVClock()
790 N = ((VClk << P) * M) / par->CrystalFreqKHz; in CalcVClock()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Daspeed-video.txt13 - clock-names: "vclk" and "eclk"
29 clock-names = "vclk", "eclk";
/OK3568_Linux_fs/kernel/drivers/gpu/drm/exynos/
H A Dexynos7_drm_decon.c50 struct clk *vclk; member
147 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); in decon_calc_clkdiv()
718 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); in decon_probe()
719 if (IS_ERR(ctx->vclk)) { in decon_probe()
721 ret = PTR_ERR(ctx->vclk); in decon_probe()
786 clk_disable_unprepare(ctx->vclk); in exynos7_decon_suspend()
820 ret = clk_prepare_enable(ctx->vclk); in exynos7_decon_resume()
822 DRM_DEV_ERROR(dev, "Failed to prepare_enable the vclk [%d]\n", in exynos7_decon_resume()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/dispnv04/
H A Darb.c193 nv04_update_arb(struct drm_device *dev, int VClk, int bpp, in nv04_update_arb() argument
204 sim_data.pclk_khz = VClk; in nv04_update_arb()
251 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) in nouveau_calc_arb() argument
256 nv04_update_arb(dev, vclk, bpp, burst, lwm); in nouveau_calc_arb()
/OK3568_Linux_fs/kernel/drivers/video/fbdev/riva/
H A Driva_hw.c610 unsigned VClk, in nv3UpdateArbitrationSettings() argument
636 sim_data.pclk_khz = VClk; in nv3UpdateArbitrationSettings()
799 unsigned VClk, in nv4UpdateArbitrationSettings() argument
826 sim_data.pclk_khz = VClk; in nv4UpdateArbitrationSettings()
1062 unsigned VClk, in nv10UpdateArbitrationSettings() argument
1091 sim_data.pclk_khz = VClk; in nv10UpdateArbitrationSettings()
1107 unsigned VClk, in nForceUpdateArbitrationSettings() argument
1147 sim_data.pclk_khz = VClk; in nForceUpdateArbitrationSettings()
1182 unsigned VClk, Freq; in CalcVClock() local
1187 VClk = (unsigned)clockIn; in CalcVClock()
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/OK3568_Linux_fs/kernel/drivers/video/fbdev/via/
H A Dvt1636.c186 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3324()
210 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3327()
227 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3364()
/OK3568_Linux_fs/kernel/drivers/video/fbdev/aty/
H A Dmach64_ct.c75 * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3
92 * - Generate the pixel clock for the LCD monitor (instead of VCLK)
218 printk(KERN_CRIT "atyfb: vclk out of range\n"); in aty_valid_pll_ct()
231 printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n", in aty_valid_pll_ct()
234 pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */ in aty_valid_pll_ct()
313 /* Reset VCLK generator */ in aty_set_pll_ct()
336 /* End VCLK generator reset */ in aty_set_pll_ct()
H A Daty128fb.c426 u32 vclk; member
1365 u32 vclk; /* in .01 MHz */ in aty128_var_to_pll() local
1369 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ in aty128_var_to_pll()
1372 if (vclk > c.ppll_max) in aty128_var_to_pll()
1373 vclk = c.ppll_max; in aty128_var_to_pll()
1374 if (vclk * 12 < c.ppll_min) in aty128_var_to_pll()
1375 vclk = c.ppll_min/12; in aty128_var_to_pll()
1379 output_freq = post_dividers[i] * vclk; in aty128_var_to_pll()
1394 pll->vclk = vclk; in aty128_var_to_pll()
1398 pll->feedback_divider, vclk, output_freq, in aty128_var_to_pll()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu8_hwmgr.c140 if (clock <= ptable->entries[i].vclk) in smu8_get_uvd_level()
148 if (clock >= ptable->entries[i].vclk) in smu8_get_uvd_level()
513 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; in smu8_upload_pptable_to_smu()
597 clock = table->entries[level].vclk; in smu8_init_uvd_limit()
599 clock = table->entries[table->count - 1].vclk; in smu8_init_uvd_limit()
1415 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu8_dpm_get_pp_table_entry()
1722 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in smu8_read_sensor() local
1756 vclk = uvd_table->entries[uvd_index].vclk; in smu8_read_sensor()
1757 *((uint32_t *)value) = vclk; in smu8_read_sensor()
1893 ptable->entries[ptable->count - 1].vclk; in smu8_dpm_update_uvd_dpm()
/OK3568_Linux_fs/kernel/drivers/media/platform/
H A Daspeed-video.c212 struct clk *vclk; member
524 clk_disable(video->vclk); in aspeed_video_off()
535 clk_enable(video->vclk); in aspeed_video_on()
1642 video->vclk = devm_clk_get(dev, "vclk"); in aspeed_video_init()
1643 if (IS_ERR(video->vclk)) { in aspeed_video_init()
1644 dev_err(dev, "Unable to get VCLK\n"); in aspeed_video_init()
1645 rc = PTR_ERR(video->vclk); in aspeed_video_init()
1649 rc = clk_prepare(video->vclk); in aspeed_video_init()
1674 clk_unprepare(video->vclk); in aspeed_video_init()
1727 clk_unprepare(video->vclk); in aspeed_video_probe()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/inc/
H A Dpower_state.h143 uint32_t VCLK; member
183 unsigned long vclk; member
/OK3568_Linux_fs/kernel/drivers/video/fbdev/sis/
H A Dinit.c2021 /* RESET VCLK */
2173 /* VCLK */
2268 SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK, in SiS_DoCalcDelay() argument
2272 unsigned int longtemp = VCLK * colordepth; in SiS_DoCalcDelay()
2288 SiS_CalcDelay(struct SiS_Private *SiS_Pr, unsigned short VCLK, in SiS_CalcDelay() argument
2293 temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0); in SiS_CalcDelay()
2294 temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1); in SiS_CalcDelay()
2306 unsigned short temp, index, VCLK, MCLK, colorth; in SiS_SetCRT1FIFO_300() local
2311 /* Get VCLK */ in SiS_SetCRT1FIFO_300()
2313 VCLK = SiS_Pr->CSRClock; in SiS_SetCRT1FIFO_300()
[all …]
/OK3568_Linux_fs/kernel/drivers/usb/misc/sisusbvga/
H A Dsisusb_init.c582 /* VCLK */
633 unsigned short data = 0, VCLK = 0, index = 0; in SiS_SetVCLKState() local
637 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetVCLKState()
640 if (VCLK >= 166) in SiS_SetVCLKState()
644 if (VCLK >= 166) in SiS_SetVCLKState()
649 if (VCLK >= 260) in SiS_SetVCLKState()
651 else if (VCLK >= 160) in SiS_SetVCLKState()
653 else if (VCLK >= 135) in SiS_SetVCLKState()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/meson/
H A Dmeson_vclk.c18 * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
34 * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
39 * Final clocks can take input for either VCLK or VCLK2, but
40 * VCLK is the preferred path for HDMI clocking and VCLK2 is the
43 * VCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.
884 /* Set VCLK div */ in meson_vclk_set()
1101 pr_err("Fatal Error, invalid HDMI vclk freq %d\n", vclk_freq); in meson_vclk_setup()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/
H A Damlogic,meson-vpu.yaml20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
53 The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/exynos/
H A Dsamsung-fimd.txt40 - samsung,invert-vclk: video clock signal is inverted
60 VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dsi.c1581 * @vclk: wanted VCLK
1591 * @optimal_vclk_div: resulting vclk post divider
1598 unsigned vclk, unsigned dclk, in si_calc_upll_dividers() argument
1613 vco_min = max(max(vco_min, vclk), dclk); in si_calc_upll_dividers()
1626 /* Calc vclk divider with current vco freq */ in si_calc_upll_dividers()
1627 vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk, in si_calc_upll_dividers()
1639 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in si_calc_upll_dividers()
1659 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in si_set_uvd_clocks() argument
1664 /* Bypass vclk and dclk with bclk */ in si_set_uvd_clocks()
1672 if (!vclk || !dclk) { in si_set_uvd_clocks()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/it66353/
H A Dit66353.c1011 static void _tx_setup_afe(u32 vclk) in _tx_setup_afe() argument
1016 // vclk = 340000UL; in _tx_setup_afe()
1017 DEBUG("_tx_setup_afe %u\r\n", vclk); in _tx_setup_afe()
1020 if (vclk > 100000UL) { // IP_VCLK05 > 50MHz in _tx_setup_afe()
1026 if (vclk > 162000UL) { // IP_VCLK05 > 81MHz in _tx_setup_afe()
1034 if (vclk > 300000UL) { // single-end swing = 520mV in _tx_setup_afe()
1045 } else if (vclk > 100000UL) { // single-end swing = 450mV in _tx_setup_afe()
1193 static void _rx_setup_afe(u32 vclk) in _rx_setup_afe() argument
1197 if (vclk >= (1024UL * 102UL)) { in _rx_setup_afe()
2432 it66353_gdev.vars.vclk = it66353_get_rx_vclk(it66353_gdev.vars.Rx_active_port); in it66353_sw_irq()
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