1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * Copyright 2008 Red Hat Inc. 4*4882a593Smuzhiyun * Copyright 2009 Jerome Glisse. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 7*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 8*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 9*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 11*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 14*4882a593Smuzhiyun * all copies or substantial portions of the Software. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * Authors: Dave Airlie 25*4882a593Smuzhiyun * Alex Deucher 26*4882a593Smuzhiyun * Jerome Glisse 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #ifndef __RADEON_ASIC_H__ 29*4882a593Smuzhiyun #define __RADEON_ASIC_H__ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * common functions 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35*4882a593Smuzhiyun void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36*4882a593Smuzhiyun uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37*4882a593Smuzhiyun void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40*4882a593Smuzhiyun void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41*4882a593Smuzhiyun uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42*4882a593Smuzhiyun void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43*4882a593Smuzhiyun void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 46*4882a593Smuzhiyun u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); 47*4882a593Smuzhiyun void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 48*4882a593Smuzhiyun u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* 51*4882a593Smuzhiyun * r100,rv100,rs100,rv200,rs200 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun struct r100_mc_save { 54*4882a593Smuzhiyun u32 GENMO_WT; 55*4882a593Smuzhiyun u32 CRTC_EXT_CNTL; 56*4882a593Smuzhiyun u32 CRTC_GEN_CNTL; 57*4882a593Smuzhiyun u32 CRTC2_GEN_CNTL; 58*4882a593Smuzhiyun u32 CUR_OFFSET; 59*4882a593Smuzhiyun u32 CUR2_OFFSET; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun int r100_init(struct radeon_device *rdev); 62*4882a593Smuzhiyun void r100_fini(struct radeon_device *rdev); 63*4882a593Smuzhiyun int r100_suspend(struct radeon_device *rdev); 64*4882a593Smuzhiyun int r100_resume(struct radeon_device *rdev); 65*4882a593Smuzhiyun void r100_vga_set_state(struct radeon_device *rdev, bool state); 66*4882a593Smuzhiyun bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 67*4882a593Smuzhiyun int r100_asic_reset(struct radeon_device *rdev, bool hard); 68*4882a593Smuzhiyun u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 69*4882a593Smuzhiyun void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 70*4882a593Smuzhiyun uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags); 71*4882a593Smuzhiyun void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, 72*4882a593Smuzhiyun uint64_t entry); 73*4882a593Smuzhiyun void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 74*4882a593Smuzhiyun int r100_irq_set(struct radeon_device *rdev); 75*4882a593Smuzhiyun int r100_irq_process(struct radeon_device *rdev); 76*4882a593Smuzhiyun void r100_fence_ring_emit(struct radeon_device *rdev, 77*4882a593Smuzhiyun struct radeon_fence *fence); 78*4882a593Smuzhiyun bool r100_semaphore_ring_emit(struct radeon_device *rdev, 79*4882a593Smuzhiyun struct radeon_ring *cp, 80*4882a593Smuzhiyun struct radeon_semaphore *semaphore, 81*4882a593Smuzhiyun bool emit_wait); 82*4882a593Smuzhiyun int r100_cs_parse(struct radeon_cs_parser *p); 83*4882a593Smuzhiyun void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 84*4882a593Smuzhiyun uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 85*4882a593Smuzhiyun struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, 86*4882a593Smuzhiyun uint64_t src_offset, 87*4882a593Smuzhiyun uint64_t dst_offset, 88*4882a593Smuzhiyun unsigned num_gpu_pages, 89*4882a593Smuzhiyun struct dma_resv *resv); 90*4882a593Smuzhiyun int r100_set_surface_reg(struct radeon_device *rdev, int reg, 91*4882a593Smuzhiyun uint32_t tiling_flags, uint32_t pitch, 92*4882a593Smuzhiyun uint32_t offset, uint32_t obj_size); 93*4882a593Smuzhiyun void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 94*4882a593Smuzhiyun void r100_bandwidth_update(struct radeon_device *rdev); 95*4882a593Smuzhiyun void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 96*4882a593Smuzhiyun int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 97*4882a593Smuzhiyun void r100_hpd_init(struct radeon_device *rdev); 98*4882a593Smuzhiyun void r100_hpd_fini(struct radeon_device *rdev); 99*4882a593Smuzhiyun bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 100*4882a593Smuzhiyun void r100_hpd_set_polarity(struct radeon_device *rdev, 101*4882a593Smuzhiyun enum radeon_hpd_id hpd); 102*4882a593Smuzhiyun int r100_debugfs_rbbm_init(struct radeon_device *rdev); 103*4882a593Smuzhiyun int r100_debugfs_cp_init(struct radeon_device *rdev); 104*4882a593Smuzhiyun void r100_cp_disable(struct radeon_device *rdev); 105*4882a593Smuzhiyun int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 106*4882a593Smuzhiyun void r100_cp_fini(struct radeon_device *rdev); 107*4882a593Smuzhiyun int r100_pci_gart_init(struct radeon_device *rdev); 108*4882a593Smuzhiyun void r100_pci_gart_fini(struct radeon_device *rdev); 109*4882a593Smuzhiyun int r100_pci_gart_enable(struct radeon_device *rdev); 110*4882a593Smuzhiyun void r100_pci_gart_disable(struct radeon_device *rdev); 111*4882a593Smuzhiyun int r100_debugfs_mc_info_init(struct radeon_device *rdev); 112*4882a593Smuzhiyun int r100_gui_wait_for_idle(struct radeon_device *rdev); 113*4882a593Smuzhiyun int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 114*4882a593Smuzhiyun void r100_irq_disable(struct radeon_device *rdev); 115*4882a593Smuzhiyun void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 116*4882a593Smuzhiyun void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 117*4882a593Smuzhiyun void r100_vram_init_sizes(struct radeon_device *rdev); 118*4882a593Smuzhiyun int r100_cp_reset(struct radeon_device *rdev); 119*4882a593Smuzhiyun void r100_vga_render_disable(struct radeon_device *rdev); 120*4882a593Smuzhiyun void r100_restore_sanity(struct radeon_device *rdev); 121*4882a593Smuzhiyun int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 122*4882a593Smuzhiyun struct radeon_cs_packet *pkt, 123*4882a593Smuzhiyun struct radeon_bo *robj); 124*4882a593Smuzhiyun int r100_cs_parse_packet0(struct radeon_cs_parser *p, 125*4882a593Smuzhiyun struct radeon_cs_packet *pkt, 126*4882a593Smuzhiyun const unsigned *auth, unsigned n, 127*4882a593Smuzhiyun radeon_packet0_check_t check); 128*4882a593Smuzhiyun int r100_cs_packet_parse(struct radeon_cs_parser *p, 129*4882a593Smuzhiyun struct radeon_cs_packet *pkt, 130*4882a593Smuzhiyun unsigned idx); 131*4882a593Smuzhiyun void r100_enable_bm(struct radeon_device *rdev); 132*4882a593Smuzhiyun void r100_set_common_regs(struct radeon_device *rdev); 133*4882a593Smuzhiyun void r100_bm_disable(struct radeon_device *rdev); 134*4882a593Smuzhiyun extern bool r100_gui_idle(struct radeon_device *rdev); 135*4882a593Smuzhiyun extern void r100_pm_misc(struct radeon_device *rdev); 136*4882a593Smuzhiyun extern void r100_pm_prepare(struct radeon_device *rdev); 137*4882a593Smuzhiyun extern void r100_pm_finish(struct radeon_device *rdev); 138*4882a593Smuzhiyun extern void r100_pm_init_profile(struct radeon_device *rdev); 139*4882a593Smuzhiyun extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 140*4882a593Smuzhiyun extern void r100_page_flip(struct radeon_device *rdev, int crtc, 141*4882a593Smuzhiyun u64 crtc_base, bool async); 142*4882a593Smuzhiyun extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc); 143*4882a593Smuzhiyun extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 144*4882a593Smuzhiyun extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun u32 r100_gfx_get_rptr(struct radeon_device *rdev, 147*4882a593Smuzhiyun struct radeon_ring *ring); 148*4882a593Smuzhiyun u32 r100_gfx_get_wptr(struct radeon_device *rdev, 149*4882a593Smuzhiyun struct radeon_ring *ring); 150*4882a593Smuzhiyun void r100_gfx_set_wptr(struct radeon_device *rdev, 151*4882a593Smuzhiyun struct radeon_ring *ring); 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* 154*4882a593Smuzhiyun * r200,rv250,rs300,rv280 155*4882a593Smuzhiyun */ 156*4882a593Smuzhiyun struct radeon_fence *r200_copy_dma(struct radeon_device *rdev, 157*4882a593Smuzhiyun uint64_t src_offset, 158*4882a593Smuzhiyun uint64_t dst_offset, 159*4882a593Smuzhiyun unsigned num_gpu_pages, 160*4882a593Smuzhiyun struct dma_resv *resv); 161*4882a593Smuzhiyun void r200_set_safe_registers(struct radeon_device *rdev); 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* 164*4882a593Smuzhiyun * r300,r350,rv350,rv380 165*4882a593Smuzhiyun */ 166*4882a593Smuzhiyun extern int r300_init(struct radeon_device *rdev); 167*4882a593Smuzhiyun extern void r300_fini(struct radeon_device *rdev); 168*4882a593Smuzhiyun extern int r300_suspend(struct radeon_device *rdev); 169*4882a593Smuzhiyun extern int r300_resume(struct radeon_device *rdev); 170*4882a593Smuzhiyun extern int r300_asic_reset(struct radeon_device *rdev, bool hard); 171*4882a593Smuzhiyun extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 172*4882a593Smuzhiyun extern void r300_fence_ring_emit(struct radeon_device *rdev, 173*4882a593Smuzhiyun struct radeon_fence *fence); 174*4882a593Smuzhiyun extern int r300_cs_parse(struct radeon_cs_parser *p); 175*4882a593Smuzhiyun extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 176*4882a593Smuzhiyun extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags); 177*4882a593Smuzhiyun extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, 178*4882a593Smuzhiyun uint64_t entry); 179*4882a593Smuzhiyun extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 180*4882a593Smuzhiyun extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 181*4882a593Smuzhiyun extern void r300_set_reg_safe(struct radeon_device *rdev); 182*4882a593Smuzhiyun extern void r300_mc_program(struct radeon_device *rdev); 183*4882a593Smuzhiyun extern void r300_mc_init(struct radeon_device *rdev); 184*4882a593Smuzhiyun extern void r300_clock_startup(struct radeon_device *rdev); 185*4882a593Smuzhiyun extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 186*4882a593Smuzhiyun extern int rv370_pcie_gart_init(struct radeon_device *rdev); 187*4882a593Smuzhiyun extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 188*4882a593Smuzhiyun extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 189*4882a593Smuzhiyun extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 190*4882a593Smuzhiyun extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun /* 193*4882a593Smuzhiyun * r420,r423,rv410 194*4882a593Smuzhiyun */ 195*4882a593Smuzhiyun extern int r420_init(struct radeon_device *rdev); 196*4882a593Smuzhiyun extern void r420_fini(struct radeon_device *rdev); 197*4882a593Smuzhiyun extern int r420_suspend(struct radeon_device *rdev); 198*4882a593Smuzhiyun extern int r420_resume(struct radeon_device *rdev); 199*4882a593Smuzhiyun extern void r420_pm_init_profile(struct radeon_device *rdev); 200*4882a593Smuzhiyun extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 201*4882a593Smuzhiyun extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 202*4882a593Smuzhiyun extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 203*4882a593Smuzhiyun extern void r420_pipes_init(struct radeon_device *rdev); 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun /* 206*4882a593Smuzhiyun * rs400,rs480 207*4882a593Smuzhiyun */ 208*4882a593Smuzhiyun extern int rs400_init(struct radeon_device *rdev); 209*4882a593Smuzhiyun extern void rs400_fini(struct radeon_device *rdev); 210*4882a593Smuzhiyun extern int rs400_suspend(struct radeon_device *rdev); 211*4882a593Smuzhiyun extern int rs400_resume(struct radeon_device *rdev); 212*4882a593Smuzhiyun void rs400_gart_tlb_flush(struct radeon_device *rdev); 213*4882a593Smuzhiyun uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags); 214*4882a593Smuzhiyun void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, 215*4882a593Smuzhiyun uint64_t entry); 216*4882a593Smuzhiyun uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 217*4882a593Smuzhiyun void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 218*4882a593Smuzhiyun int rs400_gart_init(struct radeon_device *rdev); 219*4882a593Smuzhiyun int rs400_gart_enable(struct radeon_device *rdev); 220*4882a593Smuzhiyun void rs400_gart_adjust_size(struct radeon_device *rdev); 221*4882a593Smuzhiyun void rs400_gart_disable(struct radeon_device *rdev); 222*4882a593Smuzhiyun void rs400_gart_fini(struct radeon_device *rdev); 223*4882a593Smuzhiyun extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun /* 226*4882a593Smuzhiyun * rs600. 227*4882a593Smuzhiyun */ 228*4882a593Smuzhiyun extern int rs600_asic_reset(struct radeon_device *rdev, bool hard); 229*4882a593Smuzhiyun extern int rs600_init(struct radeon_device *rdev); 230*4882a593Smuzhiyun extern void rs600_fini(struct radeon_device *rdev); 231*4882a593Smuzhiyun extern int rs600_suspend(struct radeon_device *rdev); 232*4882a593Smuzhiyun extern int rs600_resume(struct radeon_device *rdev); 233*4882a593Smuzhiyun int rs600_irq_set(struct radeon_device *rdev); 234*4882a593Smuzhiyun int rs600_irq_process(struct radeon_device *rdev); 235*4882a593Smuzhiyun void rs600_irq_disable(struct radeon_device *rdev); 236*4882a593Smuzhiyun u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 237*4882a593Smuzhiyun void rs600_gart_tlb_flush(struct radeon_device *rdev); 238*4882a593Smuzhiyun uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags); 239*4882a593Smuzhiyun void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, 240*4882a593Smuzhiyun uint64_t entry); 241*4882a593Smuzhiyun uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 242*4882a593Smuzhiyun void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 243*4882a593Smuzhiyun void rs600_bandwidth_update(struct radeon_device *rdev); 244*4882a593Smuzhiyun void rs600_hpd_init(struct radeon_device *rdev); 245*4882a593Smuzhiyun void rs600_hpd_fini(struct radeon_device *rdev); 246*4882a593Smuzhiyun bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 247*4882a593Smuzhiyun void rs600_hpd_set_polarity(struct radeon_device *rdev, 248*4882a593Smuzhiyun enum radeon_hpd_id hpd); 249*4882a593Smuzhiyun extern void rs600_pm_misc(struct radeon_device *rdev); 250*4882a593Smuzhiyun extern void rs600_pm_prepare(struct radeon_device *rdev); 251*4882a593Smuzhiyun extern void rs600_pm_finish(struct radeon_device *rdev); 252*4882a593Smuzhiyun extern void rs600_page_flip(struct radeon_device *rdev, int crtc, 253*4882a593Smuzhiyun u64 crtc_base, bool async); 254*4882a593Smuzhiyun extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc); 255*4882a593Smuzhiyun void rs600_set_safe_registers(struct radeon_device *rdev); 256*4882a593Smuzhiyun extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); 257*4882a593Smuzhiyun extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun /* 260*4882a593Smuzhiyun * rs690,rs740 261*4882a593Smuzhiyun */ 262*4882a593Smuzhiyun int rs690_init(struct radeon_device *rdev); 263*4882a593Smuzhiyun void rs690_fini(struct radeon_device *rdev); 264*4882a593Smuzhiyun int rs690_resume(struct radeon_device *rdev); 265*4882a593Smuzhiyun int rs690_suspend(struct radeon_device *rdev); 266*4882a593Smuzhiyun uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 267*4882a593Smuzhiyun void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 268*4882a593Smuzhiyun void rs690_bandwidth_update(struct radeon_device *rdev); 269*4882a593Smuzhiyun void rs690_line_buffer_adjust(struct radeon_device *rdev, 270*4882a593Smuzhiyun struct drm_display_mode *mode1, 271*4882a593Smuzhiyun struct drm_display_mode *mode2); 272*4882a593Smuzhiyun extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun /* 275*4882a593Smuzhiyun * rv515 276*4882a593Smuzhiyun */ 277*4882a593Smuzhiyun struct rv515_mc_save { 278*4882a593Smuzhiyun u32 vga_render_control; 279*4882a593Smuzhiyun u32 vga_hdp_control; 280*4882a593Smuzhiyun bool crtc_enabled[2]; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun int rv515_init(struct radeon_device *rdev); 284*4882a593Smuzhiyun void rv515_fini(struct radeon_device *rdev); 285*4882a593Smuzhiyun uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 286*4882a593Smuzhiyun void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 287*4882a593Smuzhiyun void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 288*4882a593Smuzhiyun void rv515_bandwidth_update(struct radeon_device *rdev); 289*4882a593Smuzhiyun int rv515_resume(struct radeon_device *rdev); 290*4882a593Smuzhiyun int rv515_suspend(struct radeon_device *rdev); 291*4882a593Smuzhiyun void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 292*4882a593Smuzhiyun void rv515_vga_render_disable(struct radeon_device *rdev); 293*4882a593Smuzhiyun void rv515_set_safe_registers(struct radeon_device *rdev); 294*4882a593Smuzhiyun void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 295*4882a593Smuzhiyun void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 296*4882a593Smuzhiyun void rv515_clock_startup(struct radeon_device *rdev); 297*4882a593Smuzhiyun void rv515_debugfs(struct radeon_device *rdev); 298*4882a593Smuzhiyun int rv515_mc_wait_for_idle(struct radeon_device *rdev); 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun /* 301*4882a593Smuzhiyun * r520,rv530,rv560,rv570,r580 302*4882a593Smuzhiyun */ 303*4882a593Smuzhiyun int r520_init(struct radeon_device *rdev); 304*4882a593Smuzhiyun int r520_resume(struct radeon_device *rdev); 305*4882a593Smuzhiyun int r520_mc_wait_for_idle(struct radeon_device *rdev); 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /* 308*4882a593Smuzhiyun * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 309*4882a593Smuzhiyun */ 310*4882a593Smuzhiyun int r600_init(struct radeon_device *rdev); 311*4882a593Smuzhiyun void r600_fini(struct radeon_device *rdev); 312*4882a593Smuzhiyun int r600_suspend(struct radeon_device *rdev); 313*4882a593Smuzhiyun int r600_resume(struct radeon_device *rdev); 314*4882a593Smuzhiyun void r600_vga_set_state(struct radeon_device *rdev, bool state); 315*4882a593Smuzhiyun int r600_wb_init(struct radeon_device *rdev); 316*4882a593Smuzhiyun void r600_wb_fini(struct radeon_device *rdev); 317*4882a593Smuzhiyun void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 318*4882a593Smuzhiyun uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 319*4882a593Smuzhiyun void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 320*4882a593Smuzhiyun int r600_cs_parse(struct radeon_cs_parser *p); 321*4882a593Smuzhiyun int r600_dma_cs_parse(struct radeon_cs_parser *p); 322*4882a593Smuzhiyun void r600_fence_ring_emit(struct radeon_device *rdev, 323*4882a593Smuzhiyun struct radeon_fence *fence); 324*4882a593Smuzhiyun bool r600_semaphore_ring_emit(struct radeon_device *rdev, 325*4882a593Smuzhiyun struct radeon_ring *cp, 326*4882a593Smuzhiyun struct radeon_semaphore *semaphore, 327*4882a593Smuzhiyun bool emit_wait); 328*4882a593Smuzhiyun void r600_dma_fence_ring_emit(struct radeon_device *rdev, 329*4882a593Smuzhiyun struct radeon_fence *fence); 330*4882a593Smuzhiyun bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 331*4882a593Smuzhiyun struct radeon_ring *ring, 332*4882a593Smuzhiyun struct radeon_semaphore *semaphore, 333*4882a593Smuzhiyun bool emit_wait); 334*4882a593Smuzhiyun void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 335*4882a593Smuzhiyun bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 336*4882a593Smuzhiyun bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 337*4882a593Smuzhiyun int r600_asic_reset(struct radeon_device *rdev, bool hard); 338*4882a593Smuzhiyun int r600_set_surface_reg(struct radeon_device *rdev, int reg, 339*4882a593Smuzhiyun uint32_t tiling_flags, uint32_t pitch, 340*4882a593Smuzhiyun uint32_t offset, uint32_t obj_size); 341*4882a593Smuzhiyun void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 342*4882a593Smuzhiyun int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 343*4882a593Smuzhiyun int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 344*4882a593Smuzhiyun void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 345*4882a593Smuzhiyun int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 346*4882a593Smuzhiyun int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 347*4882a593Smuzhiyun struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, 348*4882a593Smuzhiyun uint64_t src_offset, uint64_t dst_offset, 349*4882a593Smuzhiyun unsigned num_gpu_pages, 350*4882a593Smuzhiyun struct dma_resv *resv); 351*4882a593Smuzhiyun struct radeon_fence *r600_copy_dma(struct radeon_device *rdev, 352*4882a593Smuzhiyun uint64_t src_offset, uint64_t dst_offset, 353*4882a593Smuzhiyun unsigned num_gpu_pages, 354*4882a593Smuzhiyun struct dma_resv *resv); 355*4882a593Smuzhiyun void r600_hpd_init(struct radeon_device *rdev); 356*4882a593Smuzhiyun void r600_hpd_fini(struct radeon_device *rdev); 357*4882a593Smuzhiyun bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 358*4882a593Smuzhiyun void r600_hpd_set_polarity(struct radeon_device *rdev, 359*4882a593Smuzhiyun enum radeon_hpd_id hpd); 360*4882a593Smuzhiyun extern void r600_mmio_hdp_flush(struct radeon_device *rdev); 361*4882a593Smuzhiyun extern bool r600_gui_idle(struct radeon_device *rdev); 362*4882a593Smuzhiyun extern void r600_pm_misc(struct radeon_device *rdev); 363*4882a593Smuzhiyun extern void r600_pm_init_profile(struct radeon_device *rdev); 364*4882a593Smuzhiyun extern void rs780_pm_init_profile(struct radeon_device *rdev); 365*4882a593Smuzhiyun extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); 366*4882a593Smuzhiyun extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 367*4882a593Smuzhiyun extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 368*4882a593Smuzhiyun extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 369*4882a593Smuzhiyun extern int r600_get_pcie_lanes(struct radeon_device *rdev); 370*4882a593Smuzhiyun bool r600_card_posted(struct radeon_device *rdev); 371*4882a593Smuzhiyun void r600_cp_stop(struct radeon_device *rdev); 372*4882a593Smuzhiyun int r600_cp_start(struct radeon_device *rdev); 373*4882a593Smuzhiyun void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 374*4882a593Smuzhiyun int r600_cp_resume(struct radeon_device *rdev); 375*4882a593Smuzhiyun void r600_cp_fini(struct radeon_device *rdev); 376*4882a593Smuzhiyun int r600_count_pipe_bits(uint32_t val); 377*4882a593Smuzhiyun int r600_mc_wait_for_idle(struct radeon_device *rdev); 378*4882a593Smuzhiyun int r600_pcie_gart_init(struct radeon_device *rdev); 379*4882a593Smuzhiyun void r600_scratch_init(struct radeon_device *rdev); 380*4882a593Smuzhiyun int r600_init_microcode(struct radeon_device *rdev); 381*4882a593Smuzhiyun u32 r600_gfx_get_rptr(struct radeon_device *rdev, 382*4882a593Smuzhiyun struct radeon_ring *ring); 383*4882a593Smuzhiyun u32 r600_gfx_get_wptr(struct radeon_device *rdev, 384*4882a593Smuzhiyun struct radeon_ring *ring); 385*4882a593Smuzhiyun void r600_gfx_set_wptr(struct radeon_device *rdev, 386*4882a593Smuzhiyun struct radeon_ring *ring); 387*4882a593Smuzhiyun int r600_get_allowed_info_register(struct radeon_device *rdev, 388*4882a593Smuzhiyun u32 reg, u32 *val); 389*4882a593Smuzhiyun /* r600 irq */ 390*4882a593Smuzhiyun int r600_irq_process(struct radeon_device *rdev); 391*4882a593Smuzhiyun int r600_irq_init(struct radeon_device *rdev); 392*4882a593Smuzhiyun void r600_irq_fini(struct radeon_device *rdev); 393*4882a593Smuzhiyun void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 394*4882a593Smuzhiyun int r600_irq_set(struct radeon_device *rdev); 395*4882a593Smuzhiyun void r600_irq_suspend(struct radeon_device *rdev); 396*4882a593Smuzhiyun void r600_disable_interrupts(struct radeon_device *rdev); 397*4882a593Smuzhiyun void r600_rlc_stop(struct radeon_device *rdev); 398*4882a593Smuzhiyun /* r600 audio */ 399*4882a593Smuzhiyun void r600_audio_fini(struct radeon_device *rdev); 400*4882a593Smuzhiyun void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock); 401*4882a593Smuzhiyun void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, 402*4882a593Smuzhiyun size_t size); 403*4882a593Smuzhiyun void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock); 404*4882a593Smuzhiyun void r600_hdmi_audio_workaround(struct drm_encoder *encoder); 405*4882a593Smuzhiyun int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 406*4882a593Smuzhiyun void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 407*4882a593Smuzhiyun int r600_mc_wait_for_idle(struct radeon_device *rdev); 408*4882a593Smuzhiyun u32 r600_get_xclk(struct radeon_device *rdev); 409*4882a593Smuzhiyun uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); 410*4882a593Smuzhiyun int rv6xx_get_temp(struct radeon_device *rdev); 411*4882a593Smuzhiyun int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 412*4882a593Smuzhiyun int r600_dpm_pre_set_power_state(struct radeon_device *rdev); 413*4882a593Smuzhiyun void r600_dpm_post_set_power_state(struct radeon_device *rdev); 414*4882a593Smuzhiyun int r600_dpm_late_enable(struct radeon_device *rdev); 415*4882a593Smuzhiyun /* r600 dma */ 416*4882a593Smuzhiyun uint32_t r600_dma_get_rptr(struct radeon_device *rdev, 417*4882a593Smuzhiyun struct radeon_ring *ring); 418*4882a593Smuzhiyun uint32_t r600_dma_get_wptr(struct radeon_device *rdev, 419*4882a593Smuzhiyun struct radeon_ring *ring); 420*4882a593Smuzhiyun void r600_dma_set_wptr(struct radeon_device *rdev, 421*4882a593Smuzhiyun struct radeon_ring *ring); 422*4882a593Smuzhiyun /* rv6xx dpm */ 423*4882a593Smuzhiyun int rv6xx_dpm_init(struct radeon_device *rdev); 424*4882a593Smuzhiyun int rv6xx_dpm_enable(struct radeon_device *rdev); 425*4882a593Smuzhiyun void rv6xx_dpm_disable(struct radeon_device *rdev); 426*4882a593Smuzhiyun int rv6xx_dpm_set_power_state(struct radeon_device *rdev); 427*4882a593Smuzhiyun void rv6xx_setup_asic(struct radeon_device *rdev); 428*4882a593Smuzhiyun void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev); 429*4882a593Smuzhiyun void rv6xx_dpm_fini(struct radeon_device *rdev); 430*4882a593Smuzhiyun u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low); 431*4882a593Smuzhiyun u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low); 432*4882a593Smuzhiyun void rv6xx_dpm_print_power_state(struct radeon_device *rdev, 433*4882a593Smuzhiyun struct radeon_ps *ps); 434*4882a593Smuzhiyun void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 435*4882a593Smuzhiyun struct seq_file *m); 436*4882a593Smuzhiyun int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, 437*4882a593Smuzhiyun enum radeon_dpm_forced_level level); 438*4882a593Smuzhiyun u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev); 439*4882a593Smuzhiyun u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev); 440*4882a593Smuzhiyun /* rs780 dpm */ 441*4882a593Smuzhiyun int rs780_dpm_init(struct radeon_device *rdev); 442*4882a593Smuzhiyun int rs780_dpm_enable(struct radeon_device *rdev); 443*4882a593Smuzhiyun void rs780_dpm_disable(struct radeon_device *rdev); 444*4882a593Smuzhiyun int rs780_dpm_set_power_state(struct radeon_device *rdev); 445*4882a593Smuzhiyun void rs780_dpm_setup_asic(struct radeon_device *rdev); 446*4882a593Smuzhiyun void rs780_dpm_display_configuration_changed(struct radeon_device *rdev); 447*4882a593Smuzhiyun void rs780_dpm_fini(struct radeon_device *rdev); 448*4882a593Smuzhiyun u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low); 449*4882a593Smuzhiyun u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low); 450*4882a593Smuzhiyun void rs780_dpm_print_power_state(struct radeon_device *rdev, 451*4882a593Smuzhiyun struct radeon_ps *ps); 452*4882a593Smuzhiyun void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 453*4882a593Smuzhiyun struct seq_file *m); 454*4882a593Smuzhiyun int rs780_dpm_force_performance_level(struct radeon_device *rdev, 455*4882a593Smuzhiyun enum radeon_dpm_forced_level level); 456*4882a593Smuzhiyun u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev); 457*4882a593Smuzhiyun u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev); 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun /* 460*4882a593Smuzhiyun * rv770,rv730,rv710,rv740 461*4882a593Smuzhiyun */ 462*4882a593Smuzhiyun int rv770_init(struct radeon_device *rdev); 463*4882a593Smuzhiyun void rv770_fini(struct radeon_device *rdev); 464*4882a593Smuzhiyun int rv770_suspend(struct radeon_device *rdev); 465*4882a593Smuzhiyun int rv770_resume(struct radeon_device *rdev); 466*4882a593Smuzhiyun void rv770_pm_misc(struct radeon_device *rdev); 467*4882a593Smuzhiyun void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base, 468*4882a593Smuzhiyun bool async); 469*4882a593Smuzhiyun bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc); 470*4882a593Smuzhiyun void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 471*4882a593Smuzhiyun void r700_cp_stop(struct radeon_device *rdev); 472*4882a593Smuzhiyun void r700_cp_fini(struct radeon_device *rdev); 473*4882a593Smuzhiyun struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev, 474*4882a593Smuzhiyun uint64_t src_offset, uint64_t dst_offset, 475*4882a593Smuzhiyun unsigned num_gpu_pages, 476*4882a593Smuzhiyun struct dma_resv *resv); 477*4882a593Smuzhiyun u32 rv770_get_xclk(struct radeon_device *rdev); 478*4882a593Smuzhiyun int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 479*4882a593Smuzhiyun int rv770_get_temp(struct radeon_device *rdev); 480*4882a593Smuzhiyun /* rv7xx pm */ 481*4882a593Smuzhiyun int rv770_dpm_init(struct radeon_device *rdev); 482*4882a593Smuzhiyun int rv770_dpm_enable(struct radeon_device *rdev); 483*4882a593Smuzhiyun int rv770_dpm_late_enable(struct radeon_device *rdev); 484*4882a593Smuzhiyun void rv770_dpm_disable(struct radeon_device *rdev); 485*4882a593Smuzhiyun int rv770_dpm_set_power_state(struct radeon_device *rdev); 486*4882a593Smuzhiyun void rv770_dpm_setup_asic(struct radeon_device *rdev); 487*4882a593Smuzhiyun void rv770_dpm_display_configuration_changed(struct radeon_device *rdev); 488*4882a593Smuzhiyun void rv770_dpm_fini(struct radeon_device *rdev); 489*4882a593Smuzhiyun u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low); 490*4882a593Smuzhiyun u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low); 491*4882a593Smuzhiyun void rv770_dpm_print_power_state(struct radeon_device *rdev, 492*4882a593Smuzhiyun struct radeon_ps *ps); 493*4882a593Smuzhiyun void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 494*4882a593Smuzhiyun struct seq_file *m); 495*4882a593Smuzhiyun int rv770_dpm_force_performance_level(struct radeon_device *rdev, 496*4882a593Smuzhiyun enum radeon_dpm_forced_level level); 497*4882a593Smuzhiyun bool rv770_dpm_vblank_too_short(struct radeon_device *rdev); 498*4882a593Smuzhiyun u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev); 499*4882a593Smuzhiyun u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev); 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun /* 502*4882a593Smuzhiyun * evergreen 503*4882a593Smuzhiyun */ 504*4882a593Smuzhiyun struct evergreen_mc_save { 505*4882a593Smuzhiyun u32 vga_render_control; 506*4882a593Smuzhiyun u32 vga_hdp_control; 507*4882a593Smuzhiyun bool crtc_enabled[RADEON_MAX_CRTCS]; 508*4882a593Smuzhiyun }; 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 511*4882a593Smuzhiyun int evergreen_init(struct radeon_device *rdev); 512*4882a593Smuzhiyun void evergreen_fini(struct radeon_device *rdev); 513*4882a593Smuzhiyun int evergreen_suspend(struct radeon_device *rdev); 514*4882a593Smuzhiyun int evergreen_resume(struct radeon_device *rdev); 515*4882a593Smuzhiyun bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 516*4882a593Smuzhiyun bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 517*4882a593Smuzhiyun int evergreen_asic_reset(struct radeon_device *rdev, bool hard); 518*4882a593Smuzhiyun void evergreen_bandwidth_update(struct radeon_device *rdev); 519*4882a593Smuzhiyun void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 520*4882a593Smuzhiyun void evergreen_hpd_init(struct radeon_device *rdev); 521*4882a593Smuzhiyun void evergreen_hpd_fini(struct radeon_device *rdev); 522*4882a593Smuzhiyun bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 523*4882a593Smuzhiyun void evergreen_hpd_set_polarity(struct radeon_device *rdev, 524*4882a593Smuzhiyun enum radeon_hpd_id hpd); 525*4882a593Smuzhiyun u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 526*4882a593Smuzhiyun int evergreen_irq_set(struct radeon_device *rdev); 527*4882a593Smuzhiyun int evergreen_irq_process(struct radeon_device *rdev); 528*4882a593Smuzhiyun extern int evergreen_cs_parse(struct radeon_cs_parser *p); 529*4882a593Smuzhiyun extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); 530*4882a593Smuzhiyun extern void evergreen_pm_misc(struct radeon_device *rdev); 531*4882a593Smuzhiyun extern void evergreen_pm_prepare(struct radeon_device *rdev); 532*4882a593Smuzhiyun extern void evergreen_pm_finish(struct radeon_device *rdev); 533*4882a593Smuzhiyun extern void sumo_pm_init_profile(struct radeon_device *rdev); 534*4882a593Smuzhiyun extern void btc_pm_init_profile(struct radeon_device *rdev); 535*4882a593Smuzhiyun int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 536*4882a593Smuzhiyun int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 537*4882a593Smuzhiyun extern void evergreen_page_flip(struct radeon_device *rdev, int crtc, 538*4882a593Smuzhiyun u64 crtc_base, bool async); 539*4882a593Smuzhiyun extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc); 540*4882a593Smuzhiyun extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); 541*4882a593Smuzhiyun void evergreen_disable_interrupt_state(struct radeon_device *rdev); 542*4882a593Smuzhiyun int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 543*4882a593Smuzhiyun void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 544*4882a593Smuzhiyun struct radeon_fence *fence); 545*4882a593Smuzhiyun void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 546*4882a593Smuzhiyun struct radeon_ib *ib); 547*4882a593Smuzhiyun struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev, 548*4882a593Smuzhiyun uint64_t src_offset, uint64_t dst_offset, 549*4882a593Smuzhiyun unsigned num_gpu_pages, 550*4882a593Smuzhiyun struct dma_resv *resv); 551*4882a593Smuzhiyun int evergreen_get_temp(struct radeon_device *rdev); 552*4882a593Smuzhiyun int evergreen_get_allowed_info_register(struct radeon_device *rdev, 553*4882a593Smuzhiyun u32 reg, u32 *val); 554*4882a593Smuzhiyun int sumo_get_temp(struct radeon_device *rdev); 555*4882a593Smuzhiyun int tn_get_temp(struct radeon_device *rdev); 556*4882a593Smuzhiyun int cypress_dpm_init(struct radeon_device *rdev); 557*4882a593Smuzhiyun void cypress_dpm_setup_asic(struct radeon_device *rdev); 558*4882a593Smuzhiyun int cypress_dpm_enable(struct radeon_device *rdev); 559*4882a593Smuzhiyun void cypress_dpm_disable(struct radeon_device *rdev); 560*4882a593Smuzhiyun int cypress_dpm_set_power_state(struct radeon_device *rdev); 561*4882a593Smuzhiyun void cypress_dpm_display_configuration_changed(struct radeon_device *rdev); 562*4882a593Smuzhiyun void cypress_dpm_fini(struct radeon_device *rdev); 563*4882a593Smuzhiyun bool cypress_dpm_vblank_too_short(struct radeon_device *rdev); 564*4882a593Smuzhiyun int btc_dpm_init(struct radeon_device *rdev); 565*4882a593Smuzhiyun void btc_dpm_setup_asic(struct radeon_device *rdev); 566*4882a593Smuzhiyun int btc_dpm_enable(struct radeon_device *rdev); 567*4882a593Smuzhiyun void btc_dpm_disable(struct radeon_device *rdev); 568*4882a593Smuzhiyun int btc_dpm_pre_set_power_state(struct radeon_device *rdev); 569*4882a593Smuzhiyun int btc_dpm_set_power_state(struct radeon_device *rdev); 570*4882a593Smuzhiyun void btc_dpm_post_set_power_state(struct radeon_device *rdev); 571*4882a593Smuzhiyun void btc_dpm_fini(struct radeon_device *rdev); 572*4882a593Smuzhiyun u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low); 573*4882a593Smuzhiyun u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low); 574*4882a593Smuzhiyun bool btc_dpm_vblank_too_short(struct radeon_device *rdev); 575*4882a593Smuzhiyun void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 576*4882a593Smuzhiyun struct seq_file *m); 577*4882a593Smuzhiyun u32 btc_dpm_get_current_sclk(struct radeon_device *rdev); 578*4882a593Smuzhiyun u32 btc_dpm_get_current_mclk(struct radeon_device *rdev); 579*4882a593Smuzhiyun int sumo_dpm_init(struct radeon_device *rdev); 580*4882a593Smuzhiyun int sumo_dpm_enable(struct radeon_device *rdev); 581*4882a593Smuzhiyun int sumo_dpm_late_enable(struct radeon_device *rdev); 582*4882a593Smuzhiyun void sumo_dpm_disable(struct radeon_device *rdev); 583*4882a593Smuzhiyun int sumo_dpm_pre_set_power_state(struct radeon_device *rdev); 584*4882a593Smuzhiyun int sumo_dpm_set_power_state(struct radeon_device *rdev); 585*4882a593Smuzhiyun void sumo_dpm_post_set_power_state(struct radeon_device *rdev); 586*4882a593Smuzhiyun void sumo_dpm_setup_asic(struct radeon_device *rdev); 587*4882a593Smuzhiyun void sumo_dpm_display_configuration_changed(struct radeon_device *rdev); 588*4882a593Smuzhiyun void sumo_dpm_fini(struct radeon_device *rdev); 589*4882a593Smuzhiyun u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low); 590*4882a593Smuzhiyun u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low); 591*4882a593Smuzhiyun void sumo_dpm_print_power_state(struct radeon_device *rdev, 592*4882a593Smuzhiyun struct radeon_ps *ps); 593*4882a593Smuzhiyun void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 594*4882a593Smuzhiyun struct seq_file *m); 595*4882a593Smuzhiyun int sumo_dpm_force_performance_level(struct radeon_device *rdev, 596*4882a593Smuzhiyun enum radeon_dpm_forced_level level); 597*4882a593Smuzhiyun u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev); 598*4882a593Smuzhiyun u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev); 599*4882a593Smuzhiyun 600*4882a593Smuzhiyun /* 601*4882a593Smuzhiyun * cayman 602*4882a593Smuzhiyun */ 603*4882a593Smuzhiyun void cayman_fence_ring_emit(struct radeon_device *rdev, 604*4882a593Smuzhiyun struct radeon_fence *fence); 605*4882a593Smuzhiyun void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 606*4882a593Smuzhiyun int cayman_init(struct radeon_device *rdev); 607*4882a593Smuzhiyun void cayman_fini(struct radeon_device *rdev); 608*4882a593Smuzhiyun int cayman_suspend(struct radeon_device *rdev); 609*4882a593Smuzhiyun int cayman_resume(struct radeon_device *rdev); 610*4882a593Smuzhiyun int cayman_asic_reset(struct radeon_device *rdev, bool hard); 611*4882a593Smuzhiyun void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 612*4882a593Smuzhiyun int cayman_vm_init(struct radeon_device *rdev); 613*4882a593Smuzhiyun void cayman_vm_fini(struct radeon_device *rdev); 614*4882a593Smuzhiyun void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 615*4882a593Smuzhiyun unsigned vm_id, uint64_t pd_addr); 616*4882a593Smuzhiyun uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 617*4882a593Smuzhiyun int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 618*4882a593Smuzhiyun int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 619*4882a593Smuzhiyun void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 620*4882a593Smuzhiyun struct radeon_ib *ib); 621*4882a593Smuzhiyun bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 622*4882a593Smuzhiyun bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 623*4882a593Smuzhiyun 624*4882a593Smuzhiyun void cayman_dma_vm_copy_pages(struct radeon_device *rdev, 625*4882a593Smuzhiyun struct radeon_ib *ib, 626*4882a593Smuzhiyun uint64_t pe, uint64_t src, 627*4882a593Smuzhiyun unsigned count); 628*4882a593Smuzhiyun void cayman_dma_vm_write_pages(struct radeon_device *rdev, 629*4882a593Smuzhiyun struct radeon_ib *ib, 630*4882a593Smuzhiyun uint64_t pe, 631*4882a593Smuzhiyun uint64_t addr, unsigned count, 632*4882a593Smuzhiyun uint32_t incr, uint32_t flags); 633*4882a593Smuzhiyun void cayman_dma_vm_set_pages(struct radeon_device *rdev, 634*4882a593Smuzhiyun struct radeon_ib *ib, 635*4882a593Smuzhiyun uint64_t pe, 636*4882a593Smuzhiyun uint64_t addr, unsigned count, 637*4882a593Smuzhiyun uint32_t incr, uint32_t flags); 638*4882a593Smuzhiyun void cayman_dma_vm_pad_ib(struct radeon_ib *ib); 639*4882a593Smuzhiyun 640*4882a593Smuzhiyun void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 641*4882a593Smuzhiyun unsigned vm_id, uint64_t pd_addr); 642*4882a593Smuzhiyun 643*4882a593Smuzhiyun u32 cayman_gfx_get_rptr(struct radeon_device *rdev, 644*4882a593Smuzhiyun struct radeon_ring *ring); 645*4882a593Smuzhiyun u32 cayman_gfx_get_wptr(struct radeon_device *rdev, 646*4882a593Smuzhiyun struct radeon_ring *ring); 647*4882a593Smuzhiyun void cayman_gfx_set_wptr(struct radeon_device *rdev, 648*4882a593Smuzhiyun struct radeon_ring *ring); 649*4882a593Smuzhiyun uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, 650*4882a593Smuzhiyun struct radeon_ring *ring); 651*4882a593Smuzhiyun uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, 652*4882a593Smuzhiyun struct radeon_ring *ring); 653*4882a593Smuzhiyun void cayman_dma_set_wptr(struct radeon_device *rdev, 654*4882a593Smuzhiyun struct radeon_ring *ring); 655*4882a593Smuzhiyun int cayman_get_allowed_info_register(struct radeon_device *rdev, 656*4882a593Smuzhiyun u32 reg, u32 *val); 657*4882a593Smuzhiyun 658*4882a593Smuzhiyun int ni_dpm_init(struct radeon_device *rdev); 659*4882a593Smuzhiyun void ni_dpm_setup_asic(struct radeon_device *rdev); 660*4882a593Smuzhiyun int ni_dpm_enable(struct radeon_device *rdev); 661*4882a593Smuzhiyun void ni_dpm_disable(struct radeon_device *rdev); 662*4882a593Smuzhiyun int ni_dpm_pre_set_power_state(struct radeon_device *rdev); 663*4882a593Smuzhiyun int ni_dpm_set_power_state(struct radeon_device *rdev); 664*4882a593Smuzhiyun void ni_dpm_post_set_power_state(struct radeon_device *rdev); 665*4882a593Smuzhiyun void ni_dpm_fini(struct radeon_device *rdev); 666*4882a593Smuzhiyun u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low); 667*4882a593Smuzhiyun u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low); 668*4882a593Smuzhiyun void ni_dpm_print_power_state(struct radeon_device *rdev, 669*4882a593Smuzhiyun struct radeon_ps *ps); 670*4882a593Smuzhiyun void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 671*4882a593Smuzhiyun struct seq_file *m); 672*4882a593Smuzhiyun int ni_dpm_force_performance_level(struct radeon_device *rdev, 673*4882a593Smuzhiyun enum radeon_dpm_forced_level level); 674*4882a593Smuzhiyun bool ni_dpm_vblank_too_short(struct radeon_device *rdev); 675*4882a593Smuzhiyun u32 ni_dpm_get_current_sclk(struct radeon_device *rdev); 676*4882a593Smuzhiyun u32 ni_dpm_get_current_mclk(struct radeon_device *rdev); 677*4882a593Smuzhiyun int trinity_dpm_init(struct radeon_device *rdev); 678*4882a593Smuzhiyun int trinity_dpm_enable(struct radeon_device *rdev); 679*4882a593Smuzhiyun int trinity_dpm_late_enable(struct radeon_device *rdev); 680*4882a593Smuzhiyun void trinity_dpm_disable(struct radeon_device *rdev); 681*4882a593Smuzhiyun int trinity_dpm_pre_set_power_state(struct radeon_device *rdev); 682*4882a593Smuzhiyun int trinity_dpm_set_power_state(struct radeon_device *rdev); 683*4882a593Smuzhiyun void trinity_dpm_post_set_power_state(struct radeon_device *rdev); 684*4882a593Smuzhiyun void trinity_dpm_setup_asic(struct radeon_device *rdev); 685*4882a593Smuzhiyun void trinity_dpm_display_configuration_changed(struct radeon_device *rdev); 686*4882a593Smuzhiyun void trinity_dpm_fini(struct radeon_device *rdev); 687*4882a593Smuzhiyun u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low); 688*4882a593Smuzhiyun u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low); 689*4882a593Smuzhiyun void trinity_dpm_print_power_state(struct radeon_device *rdev, 690*4882a593Smuzhiyun struct radeon_ps *ps); 691*4882a593Smuzhiyun void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 692*4882a593Smuzhiyun struct seq_file *m); 693*4882a593Smuzhiyun int trinity_dpm_force_performance_level(struct radeon_device *rdev, 694*4882a593Smuzhiyun enum radeon_dpm_forced_level level); 695*4882a593Smuzhiyun void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 696*4882a593Smuzhiyun u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev); 697*4882a593Smuzhiyun u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev); 698*4882a593Smuzhiyun int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); 699*4882a593Smuzhiyun 700*4882a593Smuzhiyun /* DCE6 - SI */ 701*4882a593Smuzhiyun void dce6_bandwidth_update(struct radeon_device *rdev); 702*4882a593Smuzhiyun void dce6_audio_fini(struct radeon_device *rdev); 703*4882a593Smuzhiyun 704*4882a593Smuzhiyun /* 705*4882a593Smuzhiyun * si 706*4882a593Smuzhiyun */ 707*4882a593Smuzhiyun void si_fence_ring_emit(struct radeon_device *rdev, 708*4882a593Smuzhiyun struct radeon_fence *fence); 709*4882a593Smuzhiyun void si_pcie_gart_tlb_flush(struct radeon_device *rdev); 710*4882a593Smuzhiyun int si_init(struct radeon_device *rdev); 711*4882a593Smuzhiyun void si_fini(struct radeon_device *rdev); 712*4882a593Smuzhiyun int si_suspend(struct radeon_device *rdev); 713*4882a593Smuzhiyun int si_resume(struct radeon_device *rdev); 714*4882a593Smuzhiyun bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 715*4882a593Smuzhiyun bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 716*4882a593Smuzhiyun int si_asic_reset(struct radeon_device *rdev, bool hard); 717*4882a593Smuzhiyun void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 718*4882a593Smuzhiyun int si_irq_set(struct radeon_device *rdev); 719*4882a593Smuzhiyun int si_irq_process(struct radeon_device *rdev); 720*4882a593Smuzhiyun int si_vm_init(struct radeon_device *rdev); 721*4882a593Smuzhiyun void si_vm_fini(struct radeon_device *rdev); 722*4882a593Smuzhiyun void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 723*4882a593Smuzhiyun unsigned vm_id, uint64_t pd_addr); 724*4882a593Smuzhiyun int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 725*4882a593Smuzhiyun struct radeon_fence *si_copy_dma(struct radeon_device *rdev, 726*4882a593Smuzhiyun uint64_t src_offset, uint64_t dst_offset, 727*4882a593Smuzhiyun unsigned num_gpu_pages, 728*4882a593Smuzhiyun struct dma_resv *resv); 729*4882a593Smuzhiyun 730*4882a593Smuzhiyun void si_dma_vm_copy_pages(struct radeon_device *rdev, 731*4882a593Smuzhiyun struct radeon_ib *ib, 732*4882a593Smuzhiyun uint64_t pe, uint64_t src, 733*4882a593Smuzhiyun unsigned count); 734*4882a593Smuzhiyun void si_dma_vm_write_pages(struct radeon_device *rdev, 735*4882a593Smuzhiyun struct radeon_ib *ib, 736*4882a593Smuzhiyun uint64_t pe, 737*4882a593Smuzhiyun uint64_t addr, unsigned count, 738*4882a593Smuzhiyun uint32_t incr, uint32_t flags); 739*4882a593Smuzhiyun void si_dma_vm_set_pages(struct radeon_device *rdev, 740*4882a593Smuzhiyun struct radeon_ib *ib, 741*4882a593Smuzhiyun uint64_t pe, 742*4882a593Smuzhiyun uint64_t addr, unsigned count, 743*4882a593Smuzhiyun uint32_t incr, uint32_t flags); 744*4882a593Smuzhiyun 745*4882a593Smuzhiyun void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 746*4882a593Smuzhiyun unsigned vm_id, uint64_t pd_addr); 747*4882a593Smuzhiyun u32 si_get_xclk(struct radeon_device *rdev); 748*4882a593Smuzhiyun uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); 749*4882a593Smuzhiyun int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 750*4882a593Smuzhiyun int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); 751*4882a593Smuzhiyun int si_get_temp(struct radeon_device *rdev); 752*4882a593Smuzhiyun int si_get_allowed_info_register(struct radeon_device *rdev, 753*4882a593Smuzhiyun u32 reg, u32 *val); 754*4882a593Smuzhiyun int si_dpm_init(struct radeon_device *rdev); 755*4882a593Smuzhiyun void si_dpm_setup_asic(struct radeon_device *rdev); 756*4882a593Smuzhiyun int si_dpm_enable(struct radeon_device *rdev); 757*4882a593Smuzhiyun int si_dpm_late_enable(struct radeon_device *rdev); 758*4882a593Smuzhiyun void si_dpm_disable(struct radeon_device *rdev); 759*4882a593Smuzhiyun int si_dpm_pre_set_power_state(struct radeon_device *rdev); 760*4882a593Smuzhiyun int si_dpm_set_power_state(struct radeon_device *rdev); 761*4882a593Smuzhiyun void si_dpm_post_set_power_state(struct radeon_device *rdev); 762*4882a593Smuzhiyun void si_dpm_fini(struct radeon_device *rdev); 763*4882a593Smuzhiyun void si_dpm_display_configuration_changed(struct radeon_device *rdev); 764*4882a593Smuzhiyun void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 765*4882a593Smuzhiyun struct seq_file *m); 766*4882a593Smuzhiyun int si_dpm_force_performance_level(struct radeon_device *rdev, 767*4882a593Smuzhiyun enum radeon_dpm_forced_level level); 768*4882a593Smuzhiyun int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 769*4882a593Smuzhiyun u32 *speed); 770*4882a593Smuzhiyun int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 771*4882a593Smuzhiyun u32 speed); 772*4882a593Smuzhiyun u32 si_fan_ctrl_get_mode(struct radeon_device *rdev); 773*4882a593Smuzhiyun void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode); 774*4882a593Smuzhiyun u32 si_dpm_get_current_sclk(struct radeon_device *rdev); 775*4882a593Smuzhiyun u32 si_dpm_get_current_mclk(struct radeon_device *rdev); 776*4882a593Smuzhiyun 777*4882a593Smuzhiyun /* DCE8 - CIK */ 778*4882a593Smuzhiyun void dce8_bandwidth_update(struct radeon_device *rdev); 779*4882a593Smuzhiyun 780*4882a593Smuzhiyun /* 781*4882a593Smuzhiyun * cik 782*4882a593Smuzhiyun */ 783*4882a593Smuzhiyun uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); 784*4882a593Smuzhiyun u32 cik_get_xclk(struct radeon_device *rdev); 785*4882a593Smuzhiyun uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 786*4882a593Smuzhiyun void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 787*4882a593Smuzhiyun int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 788*4882a593Smuzhiyun int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); 789*4882a593Smuzhiyun void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 790*4882a593Smuzhiyun struct radeon_fence *fence); 791*4882a593Smuzhiyun bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 792*4882a593Smuzhiyun struct radeon_ring *ring, 793*4882a593Smuzhiyun struct radeon_semaphore *semaphore, 794*4882a593Smuzhiyun bool emit_wait); 795*4882a593Smuzhiyun void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 796*4882a593Smuzhiyun struct radeon_fence *cik_copy_dma(struct radeon_device *rdev, 797*4882a593Smuzhiyun uint64_t src_offset, uint64_t dst_offset, 798*4882a593Smuzhiyun unsigned num_gpu_pages, 799*4882a593Smuzhiyun struct dma_resv *resv); 800*4882a593Smuzhiyun struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev, 801*4882a593Smuzhiyun uint64_t src_offset, uint64_t dst_offset, 802*4882a593Smuzhiyun unsigned num_gpu_pages, 803*4882a593Smuzhiyun struct dma_resv *resv); 804*4882a593Smuzhiyun int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 805*4882a593Smuzhiyun int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 806*4882a593Smuzhiyun bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 807*4882a593Smuzhiyun void cik_fence_gfx_ring_emit(struct radeon_device *rdev, 808*4882a593Smuzhiyun struct radeon_fence *fence); 809*4882a593Smuzhiyun void cik_fence_compute_ring_emit(struct radeon_device *rdev, 810*4882a593Smuzhiyun struct radeon_fence *fence); 811*4882a593Smuzhiyun bool cik_semaphore_ring_emit(struct radeon_device *rdev, 812*4882a593Smuzhiyun struct radeon_ring *cp, 813*4882a593Smuzhiyun struct radeon_semaphore *semaphore, 814*4882a593Smuzhiyun bool emit_wait); 815*4882a593Smuzhiyun void cik_pcie_gart_tlb_flush(struct radeon_device *rdev); 816*4882a593Smuzhiyun int cik_init(struct radeon_device *rdev); 817*4882a593Smuzhiyun void cik_fini(struct radeon_device *rdev); 818*4882a593Smuzhiyun int cik_suspend(struct radeon_device *rdev); 819*4882a593Smuzhiyun int cik_resume(struct radeon_device *rdev); 820*4882a593Smuzhiyun bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 821*4882a593Smuzhiyun int cik_asic_reset(struct radeon_device *rdev, bool hard); 822*4882a593Smuzhiyun void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 823*4882a593Smuzhiyun int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 824*4882a593Smuzhiyun int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 825*4882a593Smuzhiyun int cik_irq_set(struct radeon_device *rdev); 826*4882a593Smuzhiyun int cik_irq_process(struct radeon_device *rdev); 827*4882a593Smuzhiyun int cik_vm_init(struct radeon_device *rdev); 828*4882a593Smuzhiyun void cik_vm_fini(struct radeon_device *rdev); 829*4882a593Smuzhiyun void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 830*4882a593Smuzhiyun unsigned vm_id, uint64_t pd_addr); 831*4882a593Smuzhiyun 832*4882a593Smuzhiyun void cik_sdma_vm_copy_pages(struct radeon_device *rdev, 833*4882a593Smuzhiyun struct radeon_ib *ib, 834*4882a593Smuzhiyun uint64_t pe, uint64_t src, 835*4882a593Smuzhiyun unsigned count); 836*4882a593Smuzhiyun void cik_sdma_vm_write_pages(struct radeon_device *rdev, 837*4882a593Smuzhiyun struct radeon_ib *ib, 838*4882a593Smuzhiyun uint64_t pe, 839*4882a593Smuzhiyun uint64_t addr, unsigned count, 840*4882a593Smuzhiyun uint32_t incr, uint32_t flags); 841*4882a593Smuzhiyun void cik_sdma_vm_set_pages(struct radeon_device *rdev, 842*4882a593Smuzhiyun struct radeon_ib *ib, 843*4882a593Smuzhiyun uint64_t pe, 844*4882a593Smuzhiyun uint64_t addr, unsigned count, 845*4882a593Smuzhiyun uint32_t incr, uint32_t flags); 846*4882a593Smuzhiyun void cik_sdma_vm_pad_ib(struct radeon_ib *ib); 847*4882a593Smuzhiyun 848*4882a593Smuzhiyun void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 849*4882a593Smuzhiyun unsigned vm_id, uint64_t pd_addr); 850*4882a593Smuzhiyun int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 851*4882a593Smuzhiyun u32 cik_gfx_get_rptr(struct radeon_device *rdev, 852*4882a593Smuzhiyun struct radeon_ring *ring); 853*4882a593Smuzhiyun u32 cik_gfx_get_wptr(struct radeon_device *rdev, 854*4882a593Smuzhiyun struct radeon_ring *ring); 855*4882a593Smuzhiyun void cik_gfx_set_wptr(struct radeon_device *rdev, 856*4882a593Smuzhiyun struct radeon_ring *ring); 857*4882a593Smuzhiyun u32 cik_compute_get_rptr(struct radeon_device *rdev, 858*4882a593Smuzhiyun struct radeon_ring *ring); 859*4882a593Smuzhiyun u32 cik_compute_get_wptr(struct radeon_device *rdev, 860*4882a593Smuzhiyun struct radeon_ring *ring); 861*4882a593Smuzhiyun void cik_compute_set_wptr(struct radeon_device *rdev, 862*4882a593Smuzhiyun struct radeon_ring *ring); 863*4882a593Smuzhiyun u32 cik_sdma_get_rptr(struct radeon_device *rdev, 864*4882a593Smuzhiyun struct radeon_ring *ring); 865*4882a593Smuzhiyun u32 cik_sdma_get_wptr(struct radeon_device *rdev, 866*4882a593Smuzhiyun struct radeon_ring *ring); 867*4882a593Smuzhiyun void cik_sdma_set_wptr(struct radeon_device *rdev, 868*4882a593Smuzhiyun struct radeon_ring *ring); 869*4882a593Smuzhiyun int ci_get_temp(struct radeon_device *rdev); 870*4882a593Smuzhiyun int kv_get_temp(struct radeon_device *rdev); 871*4882a593Smuzhiyun int cik_get_allowed_info_register(struct radeon_device *rdev, 872*4882a593Smuzhiyun u32 reg, u32 *val); 873*4882a593Smuzhiyun 874*4882a593Smuzhiyun int ci_dpm_init(struct radeon_device *rdev); 875*4882a593Smuzhiyun int ci_dpm_enable(struct radeon_device *rdev); 876*4882a593Smuzhiyun int ci_dpm_late_enable(struct radeon_device *rdev); 877*4882a593Smuzhiyun void ci_dpm_disable(struct radeon_device *rdev); 878*4882a593Smuzhiyun int ci_dpm_pre_set_power_state(struct radeon_device *rdev); 879*4882a593Smuzhiyun int ci_dpm_set_power_state(struct radeon_device *rdev); 880*4882a593Smuzhiyun void ci_dpm_post_set_power_state(struct radeon_device *rdev); 881*4882a593Smuzhiyun void ci_dpm_setup_asic(struct radeon_device *rdev); 882*4882a593Smuzhiyun void ci_dpm_display_configuration_changed(struct radeon_device *rdev); 883*4882a593Smuzhiyun void ci_dpm_fini(struct radeon_device *rdev); 884*4882a593Smuzhiyun u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low); 885*4882a593Smuzhiyun u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low); 886*4882a593Smuzhiyun void ci_dpm_print_power_state(struct radeon_device *rdev, 887*4882a593Smuzhiyun struct radeon_ps *ps); 888*4882a593Smuzhiyun void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 889*4882a593Smuzhiyun struct seq_file *m); 890*4882a593Smuzhiyun int ci_dpm_force_performance_level(struct radeon_device *rdev, 891*4882a593Smuzhiyun enum radeon_dpm_forced_level level); 892*4882a593Smuzhiyun bool ci_dpm_vblank_too_short(struct radeon_device *rdev); 893*4882a593Smuzhiyun void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 894*4882a593Smuzhiyun u32 ci_dpm_get_current_sclk(struct radeon_device *rdev); 895*4882a593Smuzhiyun u32 ci_dpm_get_current_mclk(struct radeon_device *rdev); 896*4882a593Smuzhiyun 897*4882a593Smuzhiyun int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 898*4882a593Smuzhiyun u32 *speed); 899*4882a593Smuzhiyun int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 900*4882a593Smuzhiyun u32 speed); 901*4882a593Smuzhiyun u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev); 902*4882a593Smuzhiyun void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode); 903*4882a593Smuzhiyun 904*4882a593Smuzhiyun int kv_dpm_init(struct radeon_device *rdev); 905*4882a593Smuzhiyun int kv_dpm_enable(struct radeon_device *rdev); 906*4882a593Smuzhiyun int kv_dpm_late_enable(struct radeon_device *rdev); 907*4882a593Smuzhiyun void kv_dpm_disable(struct radeon_device *rdev); 908*4882a593Smuzhiyun int kv_dpm_pre_set_power_state(struct radeon_device *rdev); 909*4882a593Smuzhiyun int kv_dpm_set_power_state(struct radeon_device *rdev); 910*4882a593Smuzhiyun void kv_dpm_post_set_power_state(struct radeon_device *rdev); 911*4882a593Smuzhiyun void kv_dpm_setup_asic(struct radeon_device *rdev); 912*4882a593Smuzhiyun void kv_dpm_display_configuration_changed(struct radeon_device *rdev); 913*4882a593Smuzhiyun void kv_dpm_fini(struct radeon_device *rdev); 914*4882a593Smuzhiyun u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low); 915*4882a593Smuzhiyun u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low); 916*4882a593Smuzhiyun void kv_dpm_print_power_state(struct radeon_device *rdev, 917*4882a593Smuzhiyun struct radeon_ps *ps); 918*4882a593Smuzhiyun void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 919*4882a593Smuzhiyun struct seq_file *m); 920*4882a593Smuzhiyun int kv_dpm_force_performance_level(struct radeon_device *rdev, 921*4882a593Smuzhiyun enum radeon_dpm_forced_level level); 922*4882a593Smuzhiyun void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 923*4882a593Smuzhiyun void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 924*4882a593Smuzhiyun u32 kv_dpm_get_current_sclk(struct radeon_device *rdev); 925*4882a593Smuzhiyun u32 kv_dpm_get_current_mclk(struct radeon_device *rdev); 926*4882a593Smuzhiyun 927*4882a593Smuzhiyun /* uvd v1.0 */ 928*4882a593Smuzhiyun uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, 929*4882a593Smuzhiyun struct radeon_ring *ring); 930*4882a593Smuzhiyun uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, 931*4882a593Smuzhiyun struct radeon_ring *ring); 932*4882a593Smuzhiyun void uvd_v1_0_set_wptr(struct radeon_device *rdev, 933*4882a593Smuzhiyun struct radeon_ring *ring); 934*4882a593Smuzhiyun int uvd_v1_0_resume(struct radeon_device *rdev); 935*4882a593Smuzhiyun 936*4882a593Smuzhiyun int uvd_v1_0_init(struct radeon_device *rdev); 937*4882a593Smuzhiyun void uvd_v1_0_fini(struct radeon_device *rdev); 938*4882a593Smuzhiyun int uvd_v1_0_start(struct radeon_device *rdev); 939*4882a593Smuzhiyun void uvd_v1_0_stop(struct radeon_device *rdev); 940*4882a593Smuzhiyun 941*4882a593Smuzhiyun int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 942*4882a593Smuzhiyun void uvd_v1_0_fence_emit(struct radeon_device *rdev, 943*4882a593Smuzhiyun struct radeon_fence *fence); 944*4882a593Smuzhiyun int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 945*4882a593Smuzhiyun bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev, 946*4882a593Smuzhiyun struct radeon_ring *ring, 947*4882a593Smuzhiyun struct radeon_semaphore *semaphore, 948*4882a593Smuzhiyun bool emit_wait); 949*4882a593Smuzhiyun void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun /* uvd v2.2 */ 952*4882a593Smuzhiyun int uvd_v2_2_resume(struct radeon_device *rdev); 953*4882a593Smuzhiyun void uvd_v2_2_fence_emit(struct radeon_device *rdev, 954*4882a593Smuzhiyun struct radeon_fence *fence); 955*4882a593Smuzhiyun bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev, 956*4882a593Smuzhiyun struct radeon_ring *ring, 957*4882a593Smuzhiyun struct radeon_semaphore *semaphore, 958*4882a593Smuzhiyun bool emit_wait); 959*4882a593Smuzhiyun 960*4882a593Smuzhiyun /* uvd v3.1 */ 961*4882a593Smuzhiyun bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev, 962*4882a593Smuzhiyun struct radeon_ring *ring, 963*4882a593Smuzhiyun struct radeon_semaphore *semaphore, 964*4882a593Smuzhiyun bool emit_wait); 965*4882a593Smuzhiyun 966*4882a593Smuzhiyun /* uvd v4.2 */ 967*4882a593Smuzhiyun int uvd_v4_2_resume(struct radeon_device *rdev); 968*4882a593Smuzhiyun 969*4882a593Smuzhiyun /* vce v1.0 */ 970*4882a593Smuzhiyun uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev, 971*4882a593Smuzhiyun struct radeon_ring *ring); 972*4882a593Smuzhiyun uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, 973*4882a593Smuzhiyun struct radeon_ring *ring); 974*4882a593Smuzhiyun void vce_v1_0_set_wptr(struct radeon_device *rdev, 975*4882a593Smuzhiyun struct radeon_ring *ring); 976*4882a593Smuzhiyun int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data); 977*4882a593Smuzhiyun unsigned vce_v1_0_bo_size(struct radeon_device *rdev); 978*4882a593Smuzhiyun int vce_v1_0_resume(struct radeon_device *rdev); 979*4882a593Smuzhiyun int vce_v1_0_init(struct radeon_device *rdev); 980*4882a593Smuzhiyun int vce_v1_0_start(struct radeon_device *rdev); 981*4882a593Smuzhiyun 982*4882a593Smuzhiyun /* vce v2.0 */ 983*4882a593Smuzhiyun unsigned vce_v2_0_bo_size(struct radeon_device *rdev); 984*4882a593Smuzhiyun int vce_v2_0_resume(struct radeon_device *rdev); 985*4882a593Smuzhiyun 986*4882a593Smuzhiyun #endif 987