1581  * @vclk: wanted VCLK
1591  * @optimal_vclk_div: resulting vclk post divider
1598 				 unsigned vclk, unsigned dclk,  in si_calc_upll_dividers()  argument
1613 	vco_min = max(max(vco_min, vclk), dclk);  in si_calc_upll_dividers()
1626 		/* Calc vclk divider with current vco freq */  in si_calc_upll_dividers()
1627 		vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk,  in si_calc_upll_dividers()
1639 		score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);  in si_calc_upll_dividers()
1659 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)  in si_set_uvd_clocks()  argument
1664 	/* Bypass vclk and dclk with bclk */  in si_set_uvd_clocks()
1672 	if (!vclk || !dclk) {  in si_set_uvd_clocks()
1677 	r = si_calc_upll_dividers(adev, vclk, dclk, 125000, 250000,  in si_set_uvd_clocks()
1740 	/* Switch VCLK and DCLK selection */  in si_set_uvd_clocks()
1864 	/* Switch VCLK and DCLK selection */  in si_set_vce_clocks()