xref: /OK3568_Linux_fs/kernel/drivers/video/fbdev/via/vt1636.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4*4882a593Smuzhiyun  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/via-core.h>
9*4882a593Smuzhiyun #include <linux/via_i2c.h>
10*4882a593Smuzhiyun #include "global.h"
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun static const struct IODATA common_init_data[] = {
13*4882a593Smuzhiyun /*  Index, Mask, Value */
14*4882a593Smuzhiyun 	/* Set panel power sequence timing */
15*4882a593Smuzhiyun 	{0x10, 0xC0, 0x00},
16*4882a593Smuzhiyun 	/* T1: VDD on - Data on. Each increment is 1 ms. (50ms = 031h) */
17*4882a593Smuzhiyun 	{0x0B, 0xFF, 0x40},
18*4882a593Smuzhiyun 	/* T2: Data on - Backlight on. Each increment is 2 ms. (210ms = 068h) */
19*4882a593Smuzhiyun 	{0x0C, 0xFF, 0x31},
20*4882a593Smuzhiyun 	/* T3: Backlight off -Data off. Each increment is 2 ms. (210ms = 068h)*/
21*4882a593Smuzhiyun 	{0x0D, 0xFF, 0x31},
22*4882a593Smuzhiyun 	/* T4: Data off - VDD off. Each increment is 1 ms. (50ms = 031h) */
23*4882a593Smuzhiyun 	{0x0E, 0xFF, 0x68},
24*4882a593Smuzhiyun 	/* T5: VDD off - VDD on. Each increment is 100 ms. (500ms = 04h) */
25*4882a593Smuzhiyun 	{0x0F, 0xFF, 0x68},
26*4882a593Smuzhiyun 	/* LVDS output power up */
27*4882a593Smuzhiyun 	{0x09, 0xA0, 0xA0},
28*4882a593Smuzhiyun 	/* turn on back light */
29*4882a593Smuzhiyun 	{0x10, 0x33, 0x13}
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /* Index, Mask, Value */
33*4882a593Smuzhiyun static const struct IODATA dual_channel_enable_data = {0x08, 0xF0, 0xE0};
34*4882a593Smuzhiyun static const struct IODATA single_channel_enable_data = {0x08, 0xF0, 0x00};
35*4882a593Smuzhiyun static const struct IODATA dithering_enable_data = {0x0A, 0x70, 0x50};
36*4882a593Smuzhiyun static const struct IODATA dithering_disable_data = {0x0A, 0x70, 0x00};
37*4882a593Smuzhiyun static const struct IODATA vdd_on_data = {0x10, 0x20, 0x20};
38*4882a593Smuzhiyun static const struct IODATA vdd_off_data = {0x10, 0x20, 0x00};
39*4882a593Smuzhiyun 
viafb_gpio_i2c_read_lvds(struct lvds_setting_information * plvds_setting_info,struct lvds_chip_information * plvds_chip_info,u8 index)40*4882a593Smuzhiyun u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information
41*4882a593Smuzhiyun 	*plvds_setting_info, struct lvds_chip_information *plvds_chip_info,
42*4882a593Smuzhiyun 	u8 index)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun 	u8 data;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	viafb_i2c_readbyte(plvds_chip_info->i2c_port,
47*4882a593Smuzhiyun 			   plvds_chip_info->lvds_chip_slave_addr, index, &data);
48*4882a593Smuzhiyun 	return data;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun 
viafb_gpio_i2c_write_mask_lvds(struct lvds_setting_information * plvds_setting_info,struct lvds_chip_information * plvds_chip_info,struct IODATA io_data)51*4882a593Smuzhiyun void viafb_gpio_i2c_write_mask_lvds(struct lvds_setting_information
52*4882a593Smuzhiyun 			      *plvds_setting_info, struct lvds_chip_information
53*4882a593Smuzhiyun 			      *plvds_chip_info, struct IODATA io_data)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	int index, data;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	index = io_data.Index;
58*4882a593Smuzhiyun 	data = viafb_gpio_i2c_read_lvds(plvds_setting_info, plvds_chip_info,
59*4882a593Smuzhiyun 		index);
60*4882a593Smuzhiyun 	data = (data & (~io_data.Mask)) | io_data.Data;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	viafb_i2c_writebyte(plvds_chip_info->i2c_port,
63*4882a593Smuzhiyun 			    plvds_chip_info->lvds_chip_slave_addr, index, data);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun 
viafb_init_lvds_vt1636(struct lvds_setting_information * plvds_setting_info,struct lvds_chip_information * plvds_chip_info)66*4882a593Smuzhiyun void viafb_init_lvds_vt1636(struct lvds_setting_information
67*4882a593Smuzhiyun 	*plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	int reg_num, i;
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	/* Common settings: */
72*4882a593Smuzhiyun 	reg_num = ARRAY_SIZE(common_init_data);
73*4882a593Smuzhiyun 	for (i = 0; i < reg_num; i++)
74*4882a593Smuzhiyun 		viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
75*4882a593Smuzhiyun 			plvds_chip_info, common_init_data[i]);
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	/* Input Data Mode Select */
78*4882a593Smuzhiyun 	if (plvds_setting_info->device_lcd_dualedge)
79*4882a593Smuzhiyun 		viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
80*4882a593Smuzhiyun 			plvds_chip_info, dual_channel_enable_data);
81*4882a593Smuzhiyun 	else
82*4882a593Smuzhiyun 		viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
83*4882a593Smuzhiyun 			plvds_chip_info, single_channel_enable_data);
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	if (plvds_setting_info->LCDDithering)
86*4882a593Smuzhiyun 		viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
87*4882a593Smuzhiyun 			plvds_chip_info, dithering_enable_data);
88*4882a593Smuzhiyun 	else
89*4882a593Smuzhiyun 		viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
90*4882a593Smuzhiyun 			plvds_chip_info, dithering_disable_data);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun 
viafb_enable_lvds_vt1636(struct lvds_setting_information * plvds_setting_info,struct lvds_chip_information * plvds_chip_info)93*4882a593Smuzhiyun void viafb_enable_lvds_vt1636(struct lvds_setting_information
94*4882a593Smuzhiyun 			*plvds_setting_info,
95*4882a593Smuzhiyun 			struct lvds_chip_information *plvds_chip_info)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 	viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
98*4882a593Smuzhiyun 		vdd_on_data);
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
viafb_disable_lvds_vt1636(struct lvds_setting_information * plvds_setting_info,struct lvds_chip_information * plvds_chip_info)101*4882a593Smuzhiyun void viafb_disable_lvds_vt1636(struct lvds_setting_information
102*4882a593Smuzhiyun 			 *plvds_setting_info,
103*4882a593Smuzhiyun 			 struct lvds_chip_information *plvds_chip_info)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun 	viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
106*4882a593Smuzhiyun 		vdd_off_data);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun 
viafb_lvds_identify_vt1636(u8 i2c_adapter)109*4882a593Smuzhiyun bool viafb_lvds_identify_vt1636(u8 i2c_adapter)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	u8 Buffer[2];
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	DEBUG_MSG(KERN_INFO "viafb_lvds_identify_vt1636.\n");
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	/* Sense VT1636 LVDS Transmiter */
116*4882a593Smuzhiyun 	viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
117*4882a593Smuzhiyun 		VT1636_LVDS_I2C_ADDR;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	/* Check vendor ID first: */
120*4882a593Smuzhiyun 	if (viafb_i2c_readbyte(i2c_adapter, VT1636_LVDS_I2C_ADDR,
121*4882a593Smuzhiyun 					0x00, &Buffer[0]))
122*4882a593Smuzhiyun 		return false;
123*4882a593Smuzhiyun 	viafb_i2c_readbyte(i2c_adapter, VT1636_LVDS_I2C_ADDR, 0x01, &Buffer[1]);
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	if (!((Buffer[0] == 0x06) && (Buffer[1] == 0x11)))
126*4882a593Smuzhiyun 		return false;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	/* Check Chip ID: */
129*4882a593Smuzhiyun 	viafb_i2c_readbyte(i2c_adapter, VT1636_LVDS_I2C_ADDR, 0x02, &Buffer[0]);
130*4882a593Smuzhiyun 	viafb_i2c_readbyte(i2c_adapter, VT1636_LVDS_I2C_ADDR, 0x03, &Buffer[1]);
131*4882a593Smuzhiyun 	if ((Buffer[0] == 0x45) && (Buffer[1] == 0x33)) {
132*4882a593Smuzhiyun 		viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
133*4882a593Smuzhiyun 			VT1636_LVDS;
134*4882a593Smuzhiyun 		return true;
135*4882a593Smuzhiyun 	}
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	return false;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
get_clk_range_index(u32 Clk)140*4882a593Smuzhiyun static int get_clk_range_index(u32 Clk)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	if (Clk < DPA_CLK_30M)
143*4882a593Smuzhiyun 		return DPA_CLK_RANGE_30M;
144*4882a593Smuzhiyun 	else if (Clk < DPA_CLK_50M)
145*4882a593Smuzhiyun 		return DPA_CLK_RANGE_30_50M;
146*4882a593Smuzhiyun 	else if (Clk < DPA_CLK_70M)
147*4882a593Smuzhiyun 		return DPA_CLK_RANGE_50_70M;
148*4882a593Smuzhiyun 	else if (Clk < DPA_CLK_100M)
149*4882a593Smuzhiyun 		return DPA_CLK_RANGE_70_100M;
150*4882a593Smuzhiyun 	else if (Clk < DPA_CLK_150M)
151*4882a593Smuzhiyun 		return DPA_CLK_RANGE_100_150M;
152*4882a593Smuzhiyun 	else
153*4882a593Smuzhiyun 		return DPA_CLK_RANGE_150M;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun 
set_dpa_vt1636(struct lvds_setting_information * plvds_setting_info,struct lvds_chip_information * plvds_chip_info,struct VT1636_DPA_SETTING * p_vt1636_dpa_setting)156*4882a593Smuzhiyun static void set_dpa_vt1636(struct lvds_setting_information
157*4882a593Smuzhiyun 	*plvds_setting_info, struct lvds_chip_information *plvds_chip_info,
158*4882a593Smuzhiyun 		    struct VT1636_DPA_SETTING *p_vt1636_dpa_setting)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun 	struct IODATA io_data;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	io_data.Index = 0x09;
163*4882a593Smuzhiyun 	io_data.Mask = 0x1F;
164*4882a593Smuzhiyun 	io_data.Data = p_vt1636_dpa_setting->CLK_SEL_ST1;
165*4882a593Smuzhiyun 	viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
166*4882a593Smuzhiyun 		plvds_chip_info, io_data);
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	io_data.Index = 0x08;
169*4882a593Smuzhiyun 	io_data.Mask = 0x0F;
170*4882a593Smuzhiyun 	io_data.Data = p_vt1636_dpa_setting->CLK_SEL_ST2;
171*4882a593Smuzhiyun 	viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
172*4882a593Smuzhiyun 		io_data);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun 
viafb_vt1636_patch_skew_on_vt3324(struct lvds_setting_information * plvds_setting_info,struct lvds_chip_information * plvds_chip_info)175*4882a593Smuzhiyun void viafb_vt1636_patch_skew_on_vt3324(
176*4882a593Smuzhiyun 	struct lvds_setting_information *plvds_setting_info,
177*4882a593Smuzhiyun 	struct lvds_chip_information *plvds_chip_info)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun 	struct VT1636_DPA_SETTING dpa = {0x00, 0x00}, dpa_16x12 = {0x0B, 0x03},
180*4882a593Smuzhiyun 		*pdpa;
181*4882a593Smuzhiyun 	int index;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3324.\n");
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	/* Graphics DPA settings: */
186*4882a593Smuzhiyun 	index = get_clk_range_index(plvds_setting_info->vclk);
187*4882a593Smuzhiyun 	viafb_set_dpa_gfx(plvds_chip_info->output_interface,
188*4882a593Smuzhiyun 		    &GFX_DPA_SETTING_TBL_VT3324[index]);
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	/* LVDS Transmitter DPA settings: */
191*4882a593Smuzhiyun 	if (plvds_setting_info->lcd_panel_hres == 1600 &&
192*4882a593Smuzhiyun 		plvds_setting_info->lcd_panel_vres == 1200)
193*4882a593Smuzhiyun 		pdpa = &dpa_16x12;
194*4882a593Smuzhiyun 	else
195*4882a593Smuzhiyun 		pdpa = &dpa;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	set_dpa_vt1636(plvds_setting_info, plvds_chip_info, pdpa);
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun 
viafb_vt1636_patch_skew_on_vt3327(struct lvds_setting_information * plvds_setting_info,struct lvds_chip_information * plvds_chip_info)200*4882a593Smuzhiyun void viafb_vt1636_patch_skew_on_vt3327(
201*4882a593Smuzhiyun 	struct lvds_setting_information *plvds_setting_info,
202*4882a593Smuzhiyun 	struct lvds_chip_information *plvds_chip_info)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun 	struct VT1636_DPA_SETTING dpa = {0x00, 0x00};
205*4882a593Smuzhiyun 	int index;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3327.\n");
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	/* Graphics DPA settings: */
210*4882a593Smuzhiyun 	index = get_clk_range_index(plvds_setting_info->vclk);
211*4882a593Smuzhiyun 	viafb_set_dpa_gfx(plvds_chip_info->output_interface,
212*4882a593Smuzhiyun 		    &GFX_DPA_SETTING_TBL_VT3327[index]);
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	/* LVDS Transmitter DPA settings: */
215*4882a593Smuzhiyun 	set_dpa_vt1636(plvds_setting_info, plvds_chip_info, &dpa);
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun 
viafb_vt1636_patch_skew_on_vt3364(struct lvds_setting_information * plvds_setting_info,struct lvds_chip_information * plvds_chip_info)218*4882a593Smuzhiyun void viafb_vt1636_patch_skew_on_vt3364(
219*4882a593Smuzhiyun 	struct lvds_setting_information *plvds_setting_info,
220*4882a593Smuzhiyun 	struct lvds_chip_information *plvds_chip_info)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun 	int index;
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3364.\n");
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	/* Graphics DPA settings: */
227*4882a593Smuzhiyun 	index = get_clk_range_index(plvds_setting_info->vclk);
228*4882a593Smuzhiyun 	viafb_set_dpa_gfx(plvds_chip_info->output_interface,
229*4882a593Smuzhiyun 		    &GFX_DPA_SETTING_TBL_VT3364[index]);
230*4882a593Smuzhiyun }
231