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/OK3568_Linux_fs/kernel/drivers/fpga/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds a FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
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H A Dts73xx-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Technologic Systems TS-73xx SBC FPGA loader
7 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
8 * TS-7300, heavily based on load_fpga.c in their vendor tree.
17 #include <linux/fpga/fpga-mgr.h>
44 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write_init()
46 /* Reset the FPGA */ in ts73xx_fpga_write_init()
47 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
49 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
58 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write()
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/OK3568_Linux_fs/kernel/Documentation/fpga/
H A Ddfl.rst2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
11 The Device Feature List (DFL) FPGA framework (and drivers according to
14 configure, enumerate, open and access FPGA accelerators on platforms which
16 enables system level management functions such as FPGA reconfiguration.
23 walk through these predefined data structures to enumerate FPGA features:
24 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
28 +----------+ +-->+----------+ +-->+----------+ +-->+----------+
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/OK3568_Linux_fs/kernel/drivers/watchdog/
H A Dpika_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PIKA FPGA based Watchdog Timer
29 #define DRV_NAME "PIKA-WDT"
50 void __iomem *fpga; member
71 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- in pikawdt_reset()
76 * Bit 8-11, WTCHDG_TIMEOUT_SEC: Sets the watchdog timeout value in in pikawdt_reset()
80 unsigned reset = in_be32(pikawdt_private.fpga + 0x14); in pikawdt_reset()
81 /* enable with max timeout - 15 seconds */ in pikawdt_reset()
83 out_be32(pikawdt_private.fpga + 0x14, reset); in pikawdt_reset()
118 return -EBUSY; in pikawdt_open()
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/OK3568_Linux_fs/kernel/Documentation/driver-api/
H A Dxillybus.rst2 Xillybus driver for generic FPGA interface
10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
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H A Dmen-chameleon-bus.rst30 ----------------------
34 based devices.
37 -----------------------------------------
39 The current implementation is limited to PCI and PCIe based carrier devices
43 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
44 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
46 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
47 per MCB device like PCIe based carriers with MSI or MSI-X support.
54 - The MEN Chameleon Bus itself,
55 - drivers for MCB Carrier Devices and
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/OK3568_Linux_fs/kernel/drivers/staging/gs_fpgaboot/
H A DREADME2 Linux Driver Source for Xilinx FPGA firmware download
16 - Download Xilinx FPGA firmware
17 - This module downloads Xilinx FPGA firmware using gpio pins.
21 An FPGA (Field Programmable Gate Array) is a programmable hardware that is
24 This driver provides a way to download FPGA firmware.
28 - load Xilinx FPGA bitstream format[1] firmware image file using
30 - program the Xilinx FPGA using SelectMAP (parallel) mode [2]
31 - FPGA prgram is done by gpio based bit-banging, as an example
32 - platform independent file: gs_fpgaboot.c
33 - platform dependent file: io.c
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/OK3568_Linux_fs/u-boot/cmd/
H A Dfpgad.c5 * based on cmd_mem.c
9 * SPDX-License-Identifier: GPL-2.0+
23 * FPGA Memory Display
26 * fpgad {fpga} {addr} {len}
32 unsigned int fpga; in do_fpga_md() local
42 fpga = dp_last_fpga; in do_fpga_md()
51 * FPGA is specified since argc > 2 in do_fpga_md()
53 fpga = simple_strtoul(argv[1], NULL, 16); in do_fpga_md()
74 fpga_get_reg(fpga, in do_fpga_md()
75 (u16 *)fpga_ptr[fpga] + addr in do_fpga_md()
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/OK3568_Linux_fs/kernel/include/uapi/linux/
H A Dfpga-dfl.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Header File for FPGA DFL User API
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 * The IOCTL interface for DFL based FPGA is designed for extensibility by
38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
47 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
60 * Reset the FPGA Port and its AFU. No parameters are supported.
64 * Return: 0 on success, -errno of failure
70 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
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/OK3568_Linux_fs/kernel/drivers/mcb/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 FPGA based devices. It is used to identify MCB based IP-Cores within
14 an FPGA and provide the necessary framework for instantiating drivers
21 tristate "PCI based MCB carrier"
26 This is a MCB carrier on a PCI device. Both PCI attached on-board
30 If build as a module, the module is called mcb-pci.ko
33 tristate "LPC (non PCI) based MCB carrier"
39 If build as a module, the module is called mcb-lpc.ko
/OK3568_Linux_fs/kernel/arch/powerpc/boot/
H A Debony.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on earlier code:
9 * Copyright 2002-2005 MontaVista Software Inc.
30 #define EBONY_FPGA_PATH "/plb/opb/ebc/fpga"
32 #define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash"
38 u8 *fpga; in ebony_flashsel_fixup() local
43 fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH); in ebony_flashsel_fixup()
45 if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga)) in ebony_flashsel_fixup()
46 fatal("%s has missing or invalid virtual-reg property\n\r", in ebony_flashsel_fixup()
49 fpga_reg0 = in_8(fpga); in ebony_flashsel_fixup()
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/OK3568_Linux_fs/u-boot/board/armadeus/apf27/
H A Dfpga.c2 * (C) Copyright 2002-2013
5 * based on the files by
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/imx-regs.h>
19 #include "fpga.h"
45 xilinx_desc fpga[CONFIG_FPGA_COUNT] = { variable
84 * Set the FPGA's active-low program line to the specified level
88 debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__, in fpga_pgm_fn()
95 * Set the FPGA's active-high clock line to the specified level
99 debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__, in fpga_clk_fn()
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/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/arm-none-linux-gnueabihf/libc/usr/include/linux/
H A Dfpga-dfl.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Header File for FPGA DFL User API
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 * The IOCTL interface for DFL based FPGA is designed for extensibility by
38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
47 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
60 * Reset the FPGA Port and its AFU. No parameters are supported.
64 * Return: 0 on success, -errno of failure
70 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
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/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/aarch64-none-linux-gnu/libc/usr/include/linux/
H A Dfpga-dfl.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Header File for FPGA DFL User API
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 * The IOCTL interface for DFL based FPGA is designed for extensibility by
38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
47 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
60 * Reset the FPGA Port and its AFU. No parameters are supported.
64 * Return: 0 on success, -errno of failure
70 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
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/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dgef_ppc9a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
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H A Dgef_sbc310.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00010000>; // FPGA
39 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
41 bank-width = <2>;
42 device-width = <2>;
43 #address-cells = <1>;
44 #size-cells = <1>;
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H A Dgef_sbc610.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
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H A Dge_imp3a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on: P2020 DS Device Tree Source
11 /include/ "p2020si-pre.dtsi"
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
39 bank-width = <2>;
40 device-width = <1>;
45 read-only;
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/OK3568_Linux_fs/u-boot/board/imgtec/xilfpga/
H A DREADME10 MIPSfpga is an FPGA based development platform by Imagination Technologies
11 As we are dealing with a MIPS core instantiated on an FPGA, specifications
15 Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about
18 - microAptiv UP core m14Kc
19 - 50MHz clock speed
20 - 128Mbyte DDR RAM at 0x0000_0000
21 - 8Kbyte RAM at 0x1000_0000
22 - axi_intc at 0x1020_0000
23 - axi_uart16550 at 0x1040_0000
24 - axi_gpio at 0x1060_0000
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/OK3568_Linux_fs/kernel/drivers/media/pci/cx23885/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
48 This is a video4linux driver for Conexant 23885 based
55 tristate "Altera FPGA based CI module"
59 An Altera FPGA CI module for NetUP Dual DVB-T/C RF CI card.
62 module will be called altera-ci
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dmdio-mux-multiplexer.txt5 producer, gpio mux producer or generic register based mux producer.
9 - compatible : should be "mmio-mux-multiplexer"
10 - mux-controls : mux controller node to use for operating the mux
11 - mdio-parent-bus : phandle to the parent MDIO bus.
17 Documentation/devicetree/bindings/mux/mux-controller.txt
18 and Documentation/devicetree/bindings/net/mdio-mux.txt
24 fpga@66 { // fpga connected to i2c
25 compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
26 "simple-mfd";
29 mux: mux-controller { // Mux Producer
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/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/
H A Dreset_manager_gen5.c4 * SPDX-License-Identifier: GPL-2.0+
21 /* Assert or de-assert SoCFPGA reset manager reset. */
29 reg = &reset_manager_base->mpu_mod_reset; in socfpga_per_reset()
32 reg = &reset_manager_base->per_mod_reset; in socfpga_per_reset()
35 reg = &reset_manager_base->per2_mod_reset; in socfpga_per_reset()
38 reg = &reset_manager_base->brg_mod_reset; in socfpga_per_reset()
41 reg = &reset_manager_base->misc_mod_reset; in socfpga_per_reset()
63 writel(~l4wd0, &reset_manager_base->per_mod_reset); in socfpga_per_reset_all()
64 writel(0xffffffff, &reset_manager_base->per2_mod_reset); in socfpga_per_reset_all()
68 * Release peripherals from reset based on handoff
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/OK3568_Linux_fs/kernel/arch/powerpc/platforms/86xx/
H A Dgef_sbc610.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
12 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
25 #include <asm/pci-bridge.h>
56 * There is a simple interrupt handler in the main FPGA, this needs in gef_sbc610_init_irq()
59 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic"); in gef_sbc610_init_irq()
61 printk(KERN_WARNING "SBC610: No FPGA PIC\n"); in gef_sbc610_init_irq()
82 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs"); in gef_sbc610_setup_arch()
113 /* Return the FPGA revision */
129 ('A' + gef_sbc610_get_board_rev() - 1)); in gef_sbc610_show_cpuinfo()
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/OK3568_Linux_fs/kernel/drivers/irqchip/
H A Dirq-versatile-fpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Versatile FPGA-based IRQ controllers
10 #include <linux/irqchip/versatile-fpga.h>
35 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
57 u32 mask = 1 << d->hwirq; in fpga_irq_mask()
59 writel(mask, f->base + IRQ_ENABLE_CLEAR); in fpga_irq_mask()
65 u32 mask = 1 << d->hwirq; in fpga_irq_unmask()
67 writel(mask, f->base + IRQ_ENABLE_SET); in fpga_irq_unmask()
78 status = readl(f->base + IRQ_STATUS); in fpga_irq_handle()
85 unsigned int irq = ffs(status) - 1; in fpga_irq_handle()
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/OK3568_Linux_fs/kernel/arch/powerpc/platforms/52xx/
H A Dmedia5200.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for 'media5200-platform' compatible boards.
11 * Notable characteristic of the Media5200 is the presence of an FPGA
29 { .compatible = "fsl,mpc5200-gpio", },
30 { .compatible = "mpc5200-gpio", },
34 /* FPGA register set */
38 #define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS)
72 .name = "Media5200 FPGA",
85 raw_spin_lock(&desc->lock); in media5200_irq_cascade()
86 chip->irq_mask(&desc->irq_data); in media5200_irq_cascade()
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