1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2016, Imagination Technologies Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Zubair Lutfullah Kakakhel, Zubair.Kakakhel@imgtec.com 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunMIPSfpga 8*4882a593Smuzhiyun======================================= 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunMIPSfpga is an FPGA based development platform by Imagination Technologies 11*4882a593SmuzhiyunAs we are dealing with a MIPS core instantiated on an FPGA, specifications 12*4882a593Smuzhiyunare fluid and can be varied in RTL. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunThe example project provided by IMGTEC runs on the Nexys4DDR board by 15*4882a593SmuzhiyunDigilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about 16*4882a593Smuzhiyunthe example project and the Nexys4DDR board: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- microAptiv UP core m14Kc 19*4882a593Smuzhiyun- 50MHz clock speed 20*4882a593Smuzhiyun- 128Mbyte DDR RAM at 0x0000_0000 21*4882a593Smuzhiyun- 8Kbyte RAM at 0x1000_0000 22*4882a593Smuzhiyun- axi_intc at 0x1020_0000 23*4882a593Smuzhiyun- axi_uart16550 at 0x1040_0000 24*4882a593Smuzhiyun- axi_gpio at 0x1060_0000 25*4882a593Smuzhiyun- axi_i2c at 0x10A0_0000 26*4882a593Smuzhiyun- custom_gpio at 0x10C0_0000 27*4882a593Smuzhiyun- axi_ethernetlite at 0x10E0_0000 28*4882a593Smuzhiyun- 8Kbyte BootRAM at 0x1FC0_0000 29*4882a593Smuzhiyun- 16Mbyte QPI at 0x1D00_0000 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunBoot protocol: 32*4882a593Smuzhiyun-------------- 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunThe BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000. 35*4882a593SmuzhiyunThis is for easy reprogrammibility via JTAG. 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunDDR initialization is already handled by a HW IP block. 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunWhen the example project bitstream is loaded, the cpu_reset button 40*4882a593Smuzhiyunneeds to be pressed. 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunThe bootram initializes the cache and axi_uart 43*4882a593SmuzhiyunThen checks if there is anything non 0xffff_ffff at location 0x1D40_0000 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunIf there is, then that is considered as u-boot. u-boot is copied from 46*4882a593Smuzhiyun0x1D40_0000 to memory and the bootram jumps into u-boot code. 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunAt this point, the board is ready to load the Linux kernel + buildroot initramfs 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunThis can be done in multiple ways: 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun1- JTAG load the binary and jump into it. 53*4882a593Smuzhiyun2- Load kernel stored in the QSPI flash at 0x1D80_0000 54*4882a593Smuzhiyun3- Load uImage via tftp. Ethernet works in u-boot. 55*4882a593Smuzhiyun e.g. env set server ip 192.168.154.45; dhcp uImage; bootm 56