1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * GE IMP3A Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Based on: P2020 DS Device Tree Source 8*4882a593Smuzhiyun * Copyright 2009 Freescale Semiconductor Inc. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/include/ "p2020si-pre.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "GE_IMP3A"; 15*4882a593Smuzhiyun compatible = "ge,imp3a"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun memory { 18*4882a593Smuzhiyun device_type = "memory"; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun lbc: localbus@fef05000 { 22*4882a593Smuzhiyun reg = <0 0xfef05000 0 0x1000>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun ranges = <0x0 0x0 0x0 0xff000000 0x01000000 25*4882a593Smuzhiyun 0x1 0x0 0x0 0xe0000000 0x08000000 26*4882a593Smuzhiyun 0x2 0x0 0x0 0xe8000000 0x08000000 27*4882a593Smuzhiyun 0x3 0x0 0x0 0xfc100000 0x00020000 28*4882a593Smuzhiyun 0x4 0x0 0x0 0xfc000000 0x00008000 29*4882a593Smuzhiyun 0x5 0x0 0x0 0xfc008000 0x00008000 30*4882a593Smuzhiyun 0x6 0x0 0x0 0xfee00000 0x00040000 31*4882a593Smuzhiyun 0x7 0x0 0x0 0xfee80000 0x00040000>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* nor@0,0 is a mirror of part of the memory in nor@1,0 34*4882a593Smuzhiyun nor@0,0 { 35*4882a593Smuzhiyun #address-cells = <1>; 36*4882a593Smuzhiyun #size-cells = <1>; 37*4882a593Smuzhiyun compatible = "ge,imp3a-firmware-mirror", "cfi-flash"; 38*4882a593Smuzhiyun reg = <0x0 0x0 0x1000000>; 39*4882a593Smuzhiyun bank-width = <2>; 40*4882a593Smuzhiyun device-width = <1>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun partition@0 { 43*4882a593Smuzhiyun label = "firmware"; 44*4882a593Smuzhiyun reg = <0x0 0x1000000>; 45*4882a593Smuzhiyun read-only; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun nor@1,0 { 51*4882a593Smuzhiyun #address-cells = <1>; 52*4882a593Smuzhiyun #size-cells = <1>; 53*4882a593Smuzhiyun compatible = "ge,imp3a-paged-flash", "cfi-flash"; 54*4882a593Smuzhiyun reg = <0x1 0x0 0x8000000>; 55*4882a593Smuzhiyun bank-width = <2>; 56*4882a593Smuzhiyun device-width = <1>; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun partition@0 { 59*4882a593Smuzhiyun label = "user"; 60*4882a593Smuzhiyun reg = <0x0 0x7800000>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun partition@7800000 { 64*4882a593Smuzhiyun label = "firmware"; 65*4882a593Smuzhiyun reg = <0x7800000 0x800000>; 66*4882a593Smuzhiyun read-only; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun nvram@3,0 { 71*4882a593Smuzhiyun device_type = "nvram"; 72*4882a593Smuzhiyun compatible = "simtek,stk14ca8"; 73*4882a593Smuzhiyun reg = <0x3 0x0 0x20000>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun fpga@4,0 { 77*4882a593Smuzhiyun compatible = "ge,imp3a-fpga-regs"; 78*4882a593Smuzhiyun reg = <0x4 0x0 0x20>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun gef_pic: pic@4,20 { 82*4882a593Smuzhiyun #interrupt-cells = <1>; 83*4882a593Smuzhiyun interrupt-controller; 84*4882a593Smuzhiyun device_type = "interrupt-controller"; 85*4882a593Smuzhiyun compatible = "ge,imp3a-fpga-pic", "gef,fpga-pic-1.00"; 86*4882a593Smuzhiyun reg = <0x4 0x20 0x20>; 87*4882a593Smuzhiyun interrupts = <6 7 0 0>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun gef_gpio: gpio@4,400 { 91*4882a593Smuzhiyun #gpio-cells = <2>; 92*4882a593Smuzhiyun compatible = "ge,imp3a-gpio"; 93*4882a593Smuzhiyun reg = <0x4 0x400 0x24>; 94*4882a593Smuzhiyun gpio-controller; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun wdt@4,800 { 98*4882a593Smuzhiyun compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00", 99*4882a593Smuzhiyun "gef,fpga-wdt"; 100*4882a593Smuzhiyun reg = <0x4 0x800 0x8>; 101*4882a593Smuzhiyun interrupts = <10 4>; 102*4882a593Smuzhiyun interrupt-parent = <&gef_pic>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* Second watchdog available, driver currently supports one. 106*4882a593Smuzhiyun wdt@4,808 { 107*4882a593Smuzhiyun compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00", 108*4882a593Smuzhiyun "gef,fpga-wdt"; 109*4882a593Smuzhiyun reg = <0x4 0x808 0x8>; 110*4882a593Smuzhiyun interrupts = <9 4>; 111*4882a593Smuzhiyun interrupt-parent = <&gef_pic>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun */ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun nand@6,0 { 116*4882a593Smuzhiyun compatible = "fsl,elbc-fcm-nand"; 117*4882a593Smuzhiyun reg = <0x6 0x0 0x40000>; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun nand@7,0 { 121*4882a593Smuzhiyun compatible = "fsl,elbc-fcm-nand"; 122*4882a593Smuzhiyun reg = <0x7 0x0 0x40000>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun soc: soc@fef00000 { 127*4882a593Smuzhiyun ranges = <0x0 0 0xfef00000 0x100000>; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun i2c@3000 { 130*4882a593Smuzhiyun hwmon@48 { 131*4882a593Smuzhiyun compatible = "national,lm92"; 132*4882a593Smuzhiyun reg = <0x48>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun hwmon@4c { 136*4882a593Smuzhiyun compatible = "adi,adt7461"; 137*4882a593Smuzhiyun reg = <0x4c>; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun rtc@51 { 141*4882a593Smuzhiyun compatible = "epson,rx8581"; 142*4882a593Smuzhiyun reg = <0x51>; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun eti@6b { 146*4882a593Smuzhiyun compatible = "dallas,ds1682"; 147*4882a593Smuzhiyun reg = <0x6b>; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun usb@22000 { 152*4882a593Smuzhiyun phy_type = "ulpi"; 153*4882a593Smuzhiyun dr_mode = "host"; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun mdio@24520 { 157*4882a593Smuzhiyun phy0: ethernet-phy@0 { 158*4882a593Smuzhiyun interrupt-parent = <&gef_pic>; 159*4882a593Smuzhiyun interrupts = <0xc 0x4>; 160*4882a593Smuzhiyun reg = <0x1>; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun phy1: ethernet-phy@1 { 163*4882a593Smuzhiyun interrupt-parent = <&gef_pic>; 164*4882a593Smuzhiyun interrupts = <0xb 0x4>; 165*4882a593Smuzhiyun reg = <0x2>; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun tbi0: tbi-phy@11 { 168*4882a593Smuzhiyun reg = <0x11>; 169*4882a593Smuzhiyun device_type = "tbi-phy"; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun mdio@25520 { 174*4882a593Smuzhiyun tbi1: tbi-phy@11 { 175*4882a593Smuzhiyun reg = <0x11>; 176*4882a593Smuzhiyun device_type = "tbi-phy"; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun mdio@26520 { 181*4882a593Smuzhiyun status = "disabled"; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun enet0: ethernet@24000 { 185*4882a593Smuzhiyun tbi-handle = <&tbi0>; 186*4882a593Smuzhiyun phy-handle = <&phy0>; 187*4882a593Smuzhiyun phy-connection-type = "gmii"; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun enet1: ethernet@25000 { 191*4882a593Smuzhiyun tbi-handle = <&tbi1>; 192*4882a593Smuzhiyun phy-handle = <&phy1>; 193*4882a593Smuzhiyun phy-connection-type = "gmii"; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun enet2: ethernet@26000 { 197*4882a593Smuzhiyun status = "disabled"; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun pci0: pcie@fef08000 { 202*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 203*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0 0xfe020000 0x0 0x10000>; 204*4882a593Smuzhiyun reg = <0 0xfef08000 0 0x1000>; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun pcie@0 { 207*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xc0000000 208*4882a593Smuzhiyun 0x2000000 0x0 0xc0000000 209*4882a593Smuzhiyun 0x0 0x20000000 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun 0x1000000 0x0 0x0 212*4882a593Smuzhiyun 0x1000000 0x0 0x0 213*4882a593Smuzhiyun 0x0 0x10000>; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun pci1: pcie@fef09000 { 218*4882a593Smuzhiyun reg = <0 0xfef09000 0 0x1000>; 219*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 220*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0 0xfe010000 0x0 0x10000>; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun pcie@0 { 223*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xa0000000 224*4882a593Smuzhiyun 0x2000000 0x0 0xa0000000 225*4882a593Smuzhiyun 0x0 0x20000000 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun 0x1000000 0x0 0x0 228*4882a593Smuzhiyun 0x1000000 0x0 0x0 229*4882a593Smuzhiyun 0x0 0x10000>; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun pci2: pcie@fef0a000 { 235*4882a593Smuzhiyun reg = <0 0xfef0a000 0 0x1000>; 236*4882a593Smuzhiyun ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 237*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0 0xfe000000 0x0 0x10000>; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun pcie@0 { 240*4882a593Smuzhiyun ranges = <0x2000000 0x0 0x80000000 241*4882a593Smuzhiyun 0x2000000 0x0 0x80000000 242*4882a593Smuzhiyun 0x0 0x20000000 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun 0x1000000 0x0 0x0 245*4882a593Smuzhiyun 0x1000000 0x0 0x0 246*4882a593Smuzhiyun 0x0 0x10000>; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun}; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun/include/ "p2020si-post.dtsi" 252