1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * GE SBC610 board support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Martyn Welch <martyn.welch@ge.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
10*4882a593Smuzhiyun * Copyright 2006 Freescale Semiconductor Inc.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/stddef.h>
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/pci.h>
18*4882a593Smuzhiyun #include <linux/kdev_t.h>
19*4882a593Smuzhiyun #include <linux/delay.h>
20*4882a593Smuzhiyun #include <linux/seq_file.h>
21*4882a593Smuzhiyun #include <linux/of_platform.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <asm/time.h>
24*4882a593Smuzhiyun #include <asm/machdep.h>
25*4882a593Smuzhiyun #include <asm/pci-bridge.h>
26*4882a593Smuzhiyun #include <asm/prom.h>
27*4882a593Smuzhiyun #include <mm/mmu_decl.h>
28*4882a593Smuzhiyun #include <asm/udbg.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include <asm/mpic.h>
31*4882a593Smuzhiyun #include <asm/nvram.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include <sysdev/fsl_pci.h>
34*4882a593Smuzhiyun #include <sysdev/fsl_soc.h>
35*4882a593Smuzhiyun #include <sysdev/ge/ge_pic.h>
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #include "mpc86xx.h"
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #undef DEBUG
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #ifdef DEBUG
42*4882a593Smuzhiyun #define DBG (fmt...) do { printk(KERN_ERR "SBC610: " fmt); } while (0)
43*4882a593Smuzhiyun #else
44*4882a593Smuzhiyun #define DBG (fmt...) do { } while (0)
45*4882a593Smuzhiyun #endif
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun void __iomem *sbc610_regs;
48*4882a593Smuzhiyun
gef_sbc610_init_irq(void)49*4882a593Smuzhiyun static void __init gef_sbc610_init_irq(void)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun struct device_node *cascade_node = NULL;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun mpc86xx_init_irq();
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * There is a simple interrupt handler in the main FPGA, this needs
57*4882a593Smuzhiyun * to be cascaded into the MPIC
58*4882a593Smuzhiyun */
59*4882a593Smuzhiyun cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic");
60*4882a593Smuzhiyun if (!cascade_node) {
61*4882a593Smuzhiyun printk(KERN_WARNING "SBC610: No FPGA PIC\n");
62*4882a593Smuzhiyun return;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun gef_pic_init(cascade_node);
66*4882a593Smuzhiyun of_node_put(cascade_node);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
gef_sbc610_setup_arch(void)69*4882a593Smuzhiyun static void __init gef_sbc610_setup_arch(void)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun struct device_node *regs;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun printk(KERN_INFO "GE Intelligent Platforms SBC610 6U VPX SBC\n");
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #ifdef CONFIG_SMP
76*4882a593Smuzhiyun mpc86xx_smp_init();
77*4882a593Smuzhiyun #endif
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun fsl_pci_assign_primary();
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Remap basic board registers */
82*4882a593Smuzhiyun regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
83*4882a593Smuzhiyun if (regs) {
84*4882a593Smuzhiyun sbc610_regs = of_iomap(regs, 0);
85*4882a593Smuzhiyun if (sbc610_regs == NULL)
86*4882a593Smuzhiyun printk(KERN_WARNING "Unable to map board registers\n");
87*4882a593Smuzhiyun of_node_put(regs);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #if defined(CONFIG_MMIO_NVRAM)
91*4882a593Smuzhiyun mmio_nvram_init();
92*4882a593Smuzhiyun #endif
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* Return the PCB revision */
gef_sbc610_get_pcb_rev(void)96*4882a593Smuzhiyun static unsigned int gef_sbc610_get_pcb_rev(void)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun unsigned int reg;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun reg = ioread32(sbc610_regs);
101*4882a593Smuzhiyun return (reg >> 8) & 0xff;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* Return the board (software) revision */
gef_sbc610_get_board_rev(void)105*4882a593Smuzhiyun static unsigned int gef_sbc610_get_board_rev(void)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun unsigned int reg;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun reg = ioread32(sbc610_regs);
110*4882a593Smuzhiyun return (reg >> 16) & 0xff;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* Return the FPGA revision */
gef_sbc610_get_fpga_rev(void)114*4882a593Smuzhiyun static unsigned int gef_sbc610_get_fpga_rev(void)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun unsigned int reg;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun reg = ioread32(sbc610_regs);
119*4882a593Smuzhiyun return (reg >> 24) & 0xf;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
gef_sbc610_show_cpuinfo(struct seq_file * m)122*4882a593Smuzhiyun static void gef_sbc610_show_cpuinfo(struct seq_file *m)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun uint svid = mfspr(SPRN_SVR);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun seq_printf(m, "Revision\t: %u%c\n", gef_sbc610_get_pcb_rev(),
129*4882a593Smuzhiyun ('A' + gef_sbc610_get_board_rev() - 1));
130*4882a593Smuzhiyun seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc610_get_fpga_rev());
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun seq_printf(m, "SVR\t\t: 0x%x\n", svid);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
gef_sbc610_nec_fixup(struct pci_dev * pdev)135*4882a593Smuzhiyun static void gef_sbc610_nec_fixup(struct pci_dev *pdev)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun unsigned int val;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /* Do not do the fixup on other platforms! */
140*4882a593Smuzhiyun if (!machine_is(gef_sbc610))
141*4882a593Smuzhiyun return;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun /* Ensure ports 1, 2, 3, 4 & 5 are enabled */
146*4882a593Smuzhiyun pci_read_config_dword(pdev, 0xe0, &val);
147*4882a593Smuzhiyun pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x5);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun /* System clock is 48-MHz Oscillator and EHCI Enabled. */
150*4882a593Smuzhiyun pci_write_config_dword(pdev, 0xe4, 1 << 5);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
153*4882a593Smuzhiyun gef_sbc610_nec_fixup);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /*
156*4882a593Smuzhiyun * Called very early, device-tree isn't unflattened
157*4882a593Smuzhiyun *
158*4882a593Smuzhiyun * This function is called to determine whether the BSP is compatible with the
159*4882a593Smuzhiyun * supplied device-tree, which is assumed to be the correct one for the actual
160*4882a593Smuzhiyun * board. It is expected thati, in the future, a kernel may support multiple
161*4882a593Smuzhiyun * boards.
162*4882a593Smuzhiyun */
gef_sbc610_probe(void)163*4882a593Smuzhiyun static int __init gef_sbc610_probe(void)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun if (of_machine_is_compatible("gef,sbc610"))
166*4882a593Smuzhiyun return 1;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun return 0;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun machine_arch_initcall(gef_sbc610, mpc86xx_common_publish_devices);
172*4882a593Smuzhiyun
define_machine(gef_sbc610)173*4882a593Smuzhiyun define_machine(gef_sbc610) {
174*4882a593Smuzhiyun .name = "GE SBC610",
175*4882a593Smuzhiyun .probe = gef_sbc610_probe,
176*4882a593Smuzhiyun .setup_arch = gef_sbc610_setup_arch,
177*4882a593Smuzhiyun .init_IRQ = gef_sbc610_init_irq,
178*4882a593Smuzhiyun .show_cpuinfo = gef_sbc610_show_cpuinfo,
179*4882a593Smuzhiyun .get_irq = mpic_get_irq,
180*4882a593Smuzhiyun .time_init = mpc86xx_time_init,
181*4882a593Smuzhiyun .calibrate_decr = generic_calibrate_decr,
182*4882a593Smuzhiyun .progress = udbg_progress,
183*4882a593Smuzhiyun #ifdef CONFIG_PCI
184*4882a593Smuzhiyun .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
185*4882a593Smuzhiyun #endif
186*4882a593Smuzhiyun };
187