1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2013 Altera Corporation <www.altera.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/arch/fpga_manager.h>
11*4882a593Smuzhiyun #include <asm/arch/reset_manager.h>
12*4882a593Smuzhiyun #include <asm/arch/system_manager.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static const struct socfpga_reset_manager *reset_manager_base =
17*4882a593Smuzhiyun (void *)SOCFPGA_RSTMGR_ADDRESS;
18*4882a593Smuzhiyun static const struct socfpga_system_manager *sysmgr_regs =
19*4882a593Smuzhiyun (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* Assert or de-assert SoCFPGA reset manager reset. */
socfpga_per_reset(u32 reset,int set)22*4882a593Smuzhiyun void socfpga_per_reset(u32 reset, int set)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun const u32 *reg;
25*4882a593Smuzhiyun u32 rstmgr_bank = RSTMGR_BANK(reset);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun switch (rstmgr_bank) {
28*4882a593Smuzhiyun case 0:
29*4882a593Smuzhiyun reg = &reset_manager_base->mpu_mod_reset;
30*4882a593Smuzhiyun break;
31*4882a593Smuzhiyun case 1:
32*4882a593Smuzhiyun reg = &reset_manager_base->per_mod_reset;
33*4882a593Smuzhiyun break;
34*4882a593Smuzhiyun case 2:
35*4882a593Smuzhiyun reg = &reset_manager_base->per2_mod_reset;
36*4882a593Smuzhiyun break;
37*4882a593Smuzhiyun case 3:
38*4882a593Smuzhiyun reg = &reset_manager_base->brg_mod_reset;
39*4882a593Smuzhiyun break;
40*4882a593Smuzhiyun case 4:
41*4882a593Smuzhiyun reg = &reset_manager_base->misc_mod_reset;
42*4882a593Smuzhiyun break;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun default:
45*4882a593Smuzhiyun return;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (set)
49*4882a593Smuzhiyun setbits_le32(reg, 1 << RSTMGR_RESET(reset));
50*4882a593Smuzhiyun else
51*4882a593Smuzhiyun clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * Assert reset on every peripheral but L4WD0.
56*4882a593Smuzhiyun * Watchdog must be kept intact to prevent glitches
57*4882a593Smuzhiyun * and/or hangs.
58*4882a593Smuzhiyun */
socfpga_per_reset_all(void)59*4882a593Smuzhiyun void socfpga_per_reset_all(void)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun writel(~l4wd0, &reset_manager_base->per_mod_reset);
64*4882a593Smuzhiyun writel(0xffffffff, &reset_manager_base->per2_mod_reset);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /*
68*4882a593Smuzhiyun * Release peripherals from reset based on handoff
69*4882a593Smuzhiyun */
reset_deassert_peripherals_handoff(void)70*4882a593Smuzhiyun void reset_deassert_peripherals_handoff(void)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun writel(0, &reset_manager_base->per_mod_reset);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
socfpga_bridges_reset(int enable)76*4882a593Smuzhiyun void socfpga_bridges_reset(int enable)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun /* For SoCFPGA-VT, this is NOP. */
79*4882a593Smuzhiyun return;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun #else
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
84*4882a593Smuzhiyun #define L3REGS_REMAP_HPS2FPGA_MASK 0x08
85*4882a593Smuzhiyun #define L3REGS_REMAP_OCRAM_MASK 0x01
86*4882a593Smuzhiyun
socfpga_bridges_reset(int enable)87*4882a593Smuzhiyun void socfpga_bridges_reset(int enable)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
90*4882a593Smuzhiyun L3REGS_REMAP_HPS2FPGA_MASK |
91*4882a593Smuzhiyun L3REGS_REMAP_OCRAM_MASK;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun if (enable) {
94*4882a593Smuzhiyun /* brdmodrst */
95*4882a593Smuzhiyun writel(0xffffffff, &reset_manager_base->brg_mod_reset);
96*4882a593Smuzhiyun } else {
97*4882a593Smuzhiyun writel(0, &sysmgr_regs->iswgrp_handoff[0]);
98*4882a593Smuzhiyun writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* Check signal from FPGA. */
101*4882a593Smuzhiyun if (!fpgamgr_test_fpga_ready()) {
102*4882a593Smuzhiyun /* FPGA not ready, do nothing. We allow system to boot
103*4882a593Smuzhiyun * without FPGA ready. So, return 0 instead of error. */
104*4882a593Smuzhiyun printf("%s: FPGA not ready, aborting.\n", __func__);
105*4882a593Smuzhiyun return;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* brdmodrst */
109*4882a593Smuzhiyun writel(0, &reset_manager_base->brg_mod_reset);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Remap the bridges into memory map */
112*4882a593Smuzhiyun writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun return;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun #endif
117