| /OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/ |
| H A D | mali_kbase_config_defaults.h | 132 #define DEFAULT_JS_HARD_STOP_TICKS_SS (50) /* 5s */
135 #define DEFAULT_JS_HARD_STOP_TICKS_CL (50) /* 5s */
176 * Based on 75000ms timeout at nominal 100MHz, as is required for Android - based
177 * on scaling from a 50MHz GPU system.
184 * Based on 2500ms timeout at nominal 100MHz, scaled from a 50MHz GPU system.
190 * Based on 2500ms timeout at 100MHz, scaled from a 50MHz GPU system
196 * Based on 1500ms timeout at 100MHz, scaled from a 50MHz GPU system.
202 * Based on 250ms timeout at 100MHz, scaled from a 50MHz GPU system.
208 * Based on 6000ms timeout at 100MHz, scaled from a 50MHz GPU system.
227 * GPU clock frequency (<= 100MHz).
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/scsi/ |
| H A D | aic7xxx.rst | 26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
[all …]
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| /OK3568_Linux_fs/kernel/arch/m68k/include/uapi/asm/ |
| H A D | bootinfo-hp300.h | 25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
34 #define HP_385 9 /* 33MHz 68040 */
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ |
| H A D | armada3700-periph-clock.txt | 36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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| /OK3568_Linux_fs/u-boot/doc/ |
| H A D | README.m54418twr | 118 make M54418TWR_config, or - default to spi serial flash boot, 50Mhz input clock
119 make M54418TWR_nand_mii_config, or - default to nand flash boot, mii mode, 25Mhz input clock
120 make M54418TWR_nand_rmii_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
121 …make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input c…
122 make M54418TWR_serial_mii_config, or - default to spi serial flash boot, 25Mhz input clock
123 make M54418TWR_serial_rmii_config, or - default to spi serial flash boot, 50Mhz input clock
134 CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz
135 INP CLK 50 MHz VCO CLK 500 MHz
181 cpufreq = 250 MHz
182 busfreq = 125 MHz
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| /OK3568_Linux_fs/kernel/drivers/phy/intel/ |
| H A D | phy-intel-keembay-emmc.c | 59 unsigned int mhz; in keembay_emmc_phy_power() local
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
85 if (mhz <= 200 && mhz >= 170) in keembay_emmc_phy_power()
87 else if (mhz <= 170 && mhz >= 140) in keembay_emmc_phy_power()
89 else if (mhz <= 140 && mhz >= 110) in keembay_emmc_phy_power()
91 else if (mhz <= 110 && mhz >= 80) in keembay_emmc_phy_power()
93 else if (mhz <= 80 && mhz >= 50) in keembay_emmc_phy_power()
99 if (mhz > 175) in keembay_emmc_phy_power()
100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
125 0, 50); in keembay_emmc_phy_power()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/clk/uniphier/ |
| H A D | clk-uniphier-sys.c | 24 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
25 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
83 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
84 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
85 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
86 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/am33xx/ |
| H A D | clock_am33xx.c | 61 { /* 19.2 MHz */
62 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
69 { /* 24 MHz */
70 {25, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
77 { /* 25 MHz */
78 {24, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
85 { /* 26 MHz */
86 {300, 12, 2, -1, -1, -1, -1}, /* OPP 50 */
96 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
97 {125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */
[all …]
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| /OK3568_Linux_fs/kernel/arch/arm/mach-omap2/ |
| H A D | opp2xxx.h | 123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
136 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
141 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
144 /* 2420-PRCM II 600MHz core */
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3399.h | 78 #define MHz 1000000 macro
80 #define OSC_HZ (24*MHz)
81 #define APLL_HZ (600*MHz)
82 #define GPLL_HZ (800 * MHz)
83 #define CPLL_HZ (384*MHz)
84 #define NPLL_HZ (600 * MHz)
85 #define PPLL_HZ (676*MHz)
87 #define PMU_PCLK_HZ (48*MHz)
89 #define ACLKM_CORE_HZ (300*MHz)
90 #define ATCLK_CORE_HZ (300*MHz)
[all …]
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| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3568.c | 736 con = readl(&cru->clksel_con[50]); in rk3568_bus_get_clk()
739 rate = 200 * MHz; in rk3568_bus_get_clk()
741 rate = 150 * MHz; in rk3568_bus_get_clk()
743 rate = 100 * MHz; in rk3568_bus_get_clk()
749 con = readl(&cru->clksel_con[50]); in rk3568_bus_get_clk()
752 rate = 100 * MHz; in rk3568_bus_get_clk()
754 rate = 75 * MHz; in rk3568_bus_get_clk()
756 rate = 50 * MHz; in rk3568_bus_get_clk()
775 if (rate == 200 * MHz) in rk3568_bus_set_clk()
777 else if (rate == 150 * MHz) in rk3568_bus_set_clk()
[all …]
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| H A D | clk_rk3588.c | 161 rate = 702 * MHz; in rk3588_center_get_clk()
163 rate = 396 * MHz; in rk3588_center_get_clk()
165 rate = 200 * MHz; in rk3588_center_get_clk()
174 rate = 500 * MHz; in rk3588_center_get_clk()
176 rate = 250 * MHz; in rk3588_center_get_clk()
178 rate = 100 * MHz; in rk3588_center_get_clk()
187 rate = 396 * MHz; in rk3588_center_get_clk()
189 rate = 200 * MHz; in rk3588_center_get_clk()
191 rate = 100 * MHz; in rk3588_center_get_clk()
200 rate = 200 * MHz; in rk3588_center_get_clk()
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/input/touchscreen/ |
| H A D | stmpe.txt | 15 1 -> 50 us
21 7 -> 50 ms
29 6 -> 50 ms
35 1 -> 50 mA (typical 80 mA max)
53 0 -> 1.625 MHz
54 1 -> 3.25 MHz
55 2 || 3 -> 6.5 MHz
79 /* 3.25 MHz ADC clock speed */
100 * 50 mA typical 80 mA max touchscreen drivers
|
| /OK3568_Linux_fs/kernel/Documentation/fb/ |
| H A D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
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| /OK3568_Linux_fs/kernel/drivers/ata/ |
| H A D | pata_ftide010.c | 80 /* 0 = 50 MHz, 1 = 66 MHz */
95 * reference clock which is 30 nanoseconds per unit at 66MHz and 20
96 * nanoseconds per unit at 50 MHz. The PIO timings assume 33MHz speed for
104 * word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15.
106 * multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15.
108 * word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
110 * multi word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
112 * DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz. Range 0..7.
114 * multi word DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz, Range 0..7.
116 * word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
[all …]
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| /OK3568_Linux_fs/u-boot/board/freescale/s32v234evb/ |
| H A D | clock.c | 16 * refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
70 * refclk_freq - input reference clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
192 /* setup the sys clock divider for CORE_CLK (1000MHz) */ in setup_sys_clocks()
196 /* setup the sys clock divider for CORE2_CLK (500MHz) */ in setup_sys_clocks()
199 /* setup the sys clock divider for SYS3_CLK (266 MHz) */ in setup_sys_clocks()
203 /* setup the sys clock divider for SYS6_CLK (133 Mhz) */ in setup_sys_clocks()
215 * (source: PERIPH_PLL_PHI_0/5, PERI_CLK - 80 MHz) in setup_aux_clocks()
220 /* setup the aux clock divider for LIN_CLK (40MHz) */ in setup_aux_clocks()
224 /* setup the aux clock divider for ENET_TIME_CLK (50MHz) */ in setup_aux_clocks()
228 /* setup the aux clock divider for ENET_CLK (50MHz) */ in setup_aux_clocks()
[all …]
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| /OK3568_Linux_fs/u-boot/board/samsung/odroid/ |
| H A D | odroid.c | 119 /* Set APLL to 1000MHz */ in board_clock_init()
142 * Set dividers for MOUTcore = 1000 MHz in board_clock_init()
143 * coreout = MOUT / (ratio + 1) = 1000 MHz (0) in board_clock_init()
144 * corem0 = armclk / (ratio + 1) = 333 MHz (2) in board_clock_init()
145 * corem1 = armclk / (ratio + 1) = 166 MHz (5) in board_clock_init()
146 * periph = armclk / (ratio + 1) = 1000 MHz (0) in board_clock_init()
147 * atbout = MOUT / (ratio + 1) = 200 MHz (4) in board_clock_init()
148 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) in board_clock_init()
149 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) in board_clock_init()
150 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) in board_clock_init()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/video/fbdev/ |
| H A D | macmodes.c | 36 /* 512x384, 60Hz, Non-Interlaced (15.67 MHz dot clock) */
40 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
44 /* 640x480, 67Hz, Non-Interlaced (30.0 MHz dotclock) */
48 /* 640x870, 75Hz (portrait), Non-Interlaced (57.28 MHz dot clock) */
52 /* 800x600, 56 Hz, Non-Interlaced (36.00 MHz dotclock) */
56 /* 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock) */
60 /* 800x600, 72 Hz, Non-Interlaced (50.00 MHz dotclock) */
64 /* 800x600, 75 Hz, Non-Interlaced (49.50 MHz dotclock) */
68 /* 832x624, 75Hz, Non-Interlaced (57.6 MHz dotclock) */
72 /* 1024x768, 60 Hz, Non-Interlaced (65.00 MHz dotclock) */
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-s32v234/ |
| H A D | mc_cgm_regs.h | 179 /* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
183 /* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
187 /* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
193 #define ARM_PLL_PLLDV_MFD (50)
205 /* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
209 /* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
213 /* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
217 /* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
223 #define ENET_PLL_PLLDV_MFD (50)
228 /* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
[all …]
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| /OK3568_Linux_fs/rkbin/tools/ |
| H A D | ddrbin_tool_user_guide.txt | 159 ddr2_freq(ddr2_f0_freq_mhz): ddr2 frequency, unit:MHz.
160 lp2_freq (lp2_f0_freq_mhz): lpddr2 frequency, unit:MHz.
161 ddr3_freq(ddr3_f0_freq_mhz): ddr3 frequency, unit:MHz.
162 lp3_freq (lp3_f0_freq_mhz): lpddr3 frequency, unit:MHz.
163 ddr4_freq(ddr4_f0_freq_mhz): ddr4 frequency, unit:MHz.
164 lp4_freq (lp4_f0_freq_mhz): lpddr4 frequency, unit:MHz.
165 lp4x_freq(lp4x_f0_freq_mhz): lpddr4x frequency, unit:MHz.
166 lp5_freq (lp5_f0_freq_mhz): lpddr5 frequency, unit:MHz.
171 | platform | support frequencies(MHZ) |
202 | RK3588 | LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz] |
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| /OK3568_Linux_fs/kernel/drivers/cpufreq/ |
| H A D | s5pv210-cpufreq.c | 87 /* APLL M,P,S values for 1G/800Mhz */
91 /* Use 800MHz when entering sleep mode */
275 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287 in s5pv210_target()
294 * SCLKA2M(200/1=200)->(200/4=50)Mhz in s5pv210_target()
308 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX in s5pv210_target()
309 * (200/4=50)->(667/4=166)Mhz in s5pv210_target()
322 * 3. DMC1 refresh count for 133Mhz if (index == L4) is in s5pv210_target()
324 * code. 0x287@83Mhz in s5pv210_target()
375 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */ in s5pv210_target()
393 * 7. Change souce clock from SCLKMPLL(667Mhz) in s5pv210_target()
[all …]
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| /OK3568_Linux_fs/kernel/arch/arm/mach-pxa/ |
| H A D | sleep.S | 61 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
66 @ with core operating above 91 MHz
67 @ (see Errata 50, ...processor does not exit from sleep...)
103 @ about suspending with PXBus operating above 133MHz
123 orrne r7, r7, #1 @@ 99.53MHz
150 @ need 6 13-MHz cycles before changing PWRMODE
151 @ just set frequency to 91-MHz... 6*91/13 = 42
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| /OK3568_Linux_fs/u-boot/board/siemens/rut/ |
| H A D | board.c | 232 .hfp = 50, /* no spec, "don't care" values */
233 .hbp = 50,
234 .hsw = 50,
235 .vfp = 50,
236 .vbp = 50,
237 .vsw = 50,
238 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
246 .hfp = 50, /* no spec, "don't care" values */
247 .hbp = 50,
248 .hsw = 50,
[all …]
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| /OK3568_Linux_fs/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk3308.c | 115 /* DPLL VPLL0 VPLL1 mode in 24MHz*/ in rkdclk_init()
131 /* set vpll1 in 903.168MHz vco = 1.806GHz */ in rkdclk_init()
141 /* set vpll0 in 786.432MHz vco = 3.146GHz */ in rkdclk_init()
149 /* set vpll0 in 1179.648MHz, vco = 2.359GHz*/ in rkdclk_init()
183 /* dpll default set in 1300MHz */ in rkdclk_init()
185 /* set dpll in 1584 MHz ,vco=3.168G*/ in rkdclk_init()
210 /* set aclk_bus 216.7MHz */ in rkdclk_init()
215 /* set pclk_bus 50MHz,hclk_bus 92.857MHz */ in rkdclk_init()
220 /* set crypto 92.857MHz,crypto_apk 92.857MHz */ in rkdclk_init()
228 /* set aclk_peri 216.7MHz */ in rkdclk_init()
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/ |
| H A D | intel_llc.c | 63 /* convert DDR frequency from units of 266.6MHz to bandwidth */ in get_ia_constants()
69 /* Convert GT frequency to 50 HZ units */ in get_ia_constants()
89 * ring_freq = 2 * GT. ring_freq is in 100MHz units in calc_ia_freq()
94 /* max(2 * GT, DDR). NB: GT is 50MHz units */ in calc_ia_freq()
109 * For GPU frequencies less than 750MHz, in calc_ia_freq()
|