1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * SPDX-License-Identifier: MIT
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright © 2019 Intel Corporation
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/cpufreq.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include "i915_drv.h"
10*4882a593Smuzhiyun #include "intel_gt.h"
11*4882a593Smuzhiyun #include "intel_llc.h"
12*4882a593Smuzhiyun #include "intel_sideband.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun struct ia_constants {
15*4882a593Smuzhiyun unsigned int min_gpu_freq;
16*4882a593Smuzhiyun unsigned int max_gpu_freq;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun unsigned int min_ring_freq;
19*4882a593Smuzhiyun unsigned int max_ia_freq;
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
llc_to_gt(struct intel_llc * llc)22*4882a593Smuzhiyun static struct intel_gt *llc_to_gt(struct intel_llc *llc)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun return container_of(llc, struct intel_gt, llc);
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
cpu_max_MHz(void)27*4882a593Smuzhiyun static unsigned int cpu_max_MHz(void)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun struct cpufreq_policy *policy;
30*4882a593Smuzhiyun unsigned int max_khz;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun policy = cpufreq_cpu_get(0);
33*4882a593Smuzhiyun if (policy) {
34*4882a593Smuzhiyun max_khz = policy->cpuinfo.max_freq;
35*4882a593Smuzhiyun cpufreq_cpu_put(policy);
36*4882a593Smuzhiyun } else {
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun * Default to measured freq if none found, PCU will ensure we
39*4882a593Smuzhiyun * don't go over
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun max_khz = tsc_khz;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return max_khz / 1000;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
get_ia_constants(struct intel_llc * llc,struct ia_constants * consts)47*4882a593Smuzhiyun static bool get_ia_constants(struct intel_llc *llc,
48*4882a593Smuzhiyun struct ia_constants *consts)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
51*4882a593Smuzhiyun struct intel_rps *rps = &llc_to_gt(llc)->rps;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun if (!HAS_LLC(i915) || IS_DGFX(i915))
54*4882a593Smuzhiyun return false;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (rps->max_freq <= rps->min_freq)
57*4882a593Smuzhiyun return false;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun consts->max_ia_freq = cpu_max_MHz();
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun consts->min_ring_freq =
62*4882a593Smuzhiyun intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf;
63*4882a593Smuzhiyun /* convert DDR frequency from units of 266.6MHz to bandwidth */
64*4882a593Smuzhiyun consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun consts->min_gpu_freq = rps->min_freq;
67*4882a593Smuzhiyun consts->max_gpu_freq = rps->max_freq;
68*4882a593Smuzhiyun if (INTEL_GEN(i915) >= 9) {
69*4882a593Smuzhiyun /* Convert GT frequency to 50 HZ units */
70*4882a593Smuzhiyun consts->min_gpu_freq /= GEN9_FREQ_SCALER;
71*4882a593Smuzhiyun consts->max_gpu_freq /= GEN9_FREQ_SCALER;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return true;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
calc_ia_freq(struct intel_llc * llc,unsigned int gpu_freq,const struct ia_constants * consts,unsigned int * out_ia_freq,unsigned int * out_ring_freq)77*4882a593Smuzhiyun static void calc_ia_freq(struct intel_llc *llc,
78*4882a593Smuzhiyun unsigned int gpu_freq,
79*4882a593Smuzhiyun const struct ia_constants *consts,
80*4882a593Smuzhiyun unsigned int *out_ia_freq,
81*4882a593Smuzhiyun unsigned int *out_ring_freq)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
84*4882a593Smuzhiyun const int diff = consts->max_gpu_freq - gpu_freq;
85*4882a593Smuzhiyun unsigned int ia_freq = 0, ring_freq = 0;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (INTEL_GEN(i915) >= 9) {
88*4882a593Smuzhiyun /*
89*4882a593Smuzhiyun * ring_freq = 2 * GT. ring_freq is in 100MHz units
90*4882a593Smuzhiyun * No floor required for ring frequency on SKL.
91*4882a593Smuzhiyun */
92*4882a593Smuzhiyun ring_freq = gpu_freq;
93*4882a593Smuzhiyun } else if (INTEL_GEN(i915) >= 8) {
94*4882a593Smuzhiyun /* max(2 * GT, DDR). NB: GT is 50MHz units */
95*4882a593Smuzhiyun ring_freq = max(consts->min_ring_freq, gpu_freq);
96*4882a593Smuzhiyun } else if (IS_HASWELL(i915)) {
97*4882a593Smuzhiyun ring_freq = mult_frac(gpu_freq, 5, 4);
98*4882a593Smuzhiyun ring_freq = max(consts->min_ring_freq, ring_freq);
99*4882a593Smuzhiyun /* leave ia_freq as the default, chosen by cpufreq */
100*4882a593Smuzhiyun } else {
101*4882a593Smuzhiyun const int min_freq = 15;
102*4882a593Smuzhiyun const int scale = 180;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /*
105*4882a593Smuzhiyun * On older processors, there is no separate ring
106*4882a593Smuzhiyun * clock domain, so in order to boost the bandwidth
107*4882a593Smuzhiyun * of the ring, we need to upclock the CPU (ia_freq).
108*4882a593Smuzhiyun *
109*4882a593Smuzhiyun * For GPU frequencies less than 750MHz,
110*4882a593Smuzhiyun * just use the lowest ring freq.
111*4882a593Smuzhiyun */
112*4882a593Smuzhiyun if (gpu_freq < min_freq)
113*4882a593Smuzhiyun ia_freq = 800;
114*4882a593Smuzhiyun else
115*4882a593Smuzhiyun ia_freq = consts->max_ia_freq - diff * scale / 2;
116*4882a593Smuzhiyun ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun *out_ia_freq = ia_freq;
120*4882a593Smuzhiyun *out_ring_freq = ring_freq;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
gen6_update_ring_freq(struct intel_llc * llc)123*4882a593Smuzhiyun static void gen6_update_ring_freq(struct intel_llc *llc)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
126*4882a593Smuzhiyun struct ia_constants consts;
127*4882a593Smuzhiyun unsigned int gpu_freq;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun if (!get_ia_constants(llc, &consts))
130*4882a593Smuzhiyun return;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /*
133*4882a593Smuzhiyun * For each potential GPU frequency, load a ring frequency we'd like
134*4882a593Smuzhiyun * to use for memory access. We do this by specifying the IA frequency
135*4882a593Smuzhiyun * the PCU should use as a reference to determine the ring frequency.
136*4882a593Smuzhiyun */
137*4882a593Smuzhiyun for (gpu_freq = consts.max_gpu_freq;
138*4882a593Smuzhiyun gpu_freq >= consts.min_gpu_freq;
139*4882a593Smuzhiyun gpu_freq--) {
140*4882a593Smuzhiyun unsigned int ia_freq, ring_freq;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
143*4882a593Smuzhiyun sandybridge_pcode_write(i915,
144*4882a593Smuzhiyun GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
145*4882a593Smuzhiyun ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
146*4882a593Smuzhiyun ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
147*4882a593Smuzhiyun gpu_freq);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
intel_llc_enable(struct intel_llc * llc)151*4882a593Smuzhiyun void intel_llc_enable(struct intel_llc *llc)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun gen6_update_ring_freq(llc);
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
intel_llc_disable(struct intel_llc * llc)156*4882a593Smuzhiyun void intel_llc_disable(struct intel_llc *llc)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun /* Currently there is no HW configuration to be done to disable. */
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
162*4882a593Smuzhiyun #include "selftest_llc.c"
163*4882a593Smuzhiyun #endif
164