1*4882a593Smuzhiyun* Peripheral Clock bindings for Marvell Armada 37xx SoCs 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunMarvell Armada 37xx SoCs provide peripheral clocks which are 4*4882a593Smuzhiyunused as clock source for the peripheral of the SoC. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThere are two different blocks associated to north bridge and south 7*4882a593Smuzhiyunbridge. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThe peripheral clock consumer should specify the desired clock by 10*4882a593Smuzhiyunhaving the clock ID in its "clocks" phandle cell. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunThe following is a list of provided IDs for Armada 3700 North bridge clocks: 13*4882a593SmuzhiyunID Clock name Description 14*4882a593Smuzhiyun----------------------------------- 15*4882a593Smuzhiyun0 mmc MMC controller 16*4882a593Smuzhiyun1 sata_host Sata Host 17*4882a593Smuzhiyun2 sec_at Security AT 18*4882a593Smuzhiyun3 sac_dap Security DAP 19*4882a593Smuzhiyun4 tsecm Security Engine 20*4882a593Smuzhiyun5 setm_tmx Serial Embedded Trace Module 21*4882a593Smuzhiyun6 avs Adaptive Voltage Scaling 22*4882a593Smuzhiyun7 sqf SPI 23*4882a593Smuzhiyun8 pwm PWM 24*4882a593Smuzhiyun9 i2c_2 I2C 2 25*4882a593Smuzhiyun10 i2c_1 I2C 1 26*4882a593Smuzhiyun11 ddr_phy DDR PHY 27*4882a593Smuzhiyun12 ddr_fclk DDR F clock 28*4882a593Smuzhiyun13 trace Trace 29*4882a593Smuzhiyun14 counter Counter 30*4882a593Smuzhiyun15 eip97 EIP 97 31*4882a593Smuzhiyun16 cpu CPU 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunThe following is a list of provided IDs for Armada 3700 South bridge clocks: 34*4882a593SmuzhiyunID Clock name Description 35*4882a593Smuzhiyun----------------------------------- 36*4882a593Smuzhiyun0 gbe-50 50 MHz parent clock for Gigabit Ethernet 37*4882a593Smuzhiyun1 gbe-core parent clock for Gigabit Ethernet core 38*4882a593Smuzhiyun2 gbe-125 125 MHz parent clock for Gigabit Ethernet 39*4882a593Smuzhiyun3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1 40*4882a593Smuzhiyun4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0 41*4882a593Smuzhiyun5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1 42*4882a593Smuzhiyun6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0 43*4882a593Smuzhiyun7 gbe1-core Gigabit Ethernet core port 1 44*4882a593Smuzhiyun8 gbe0-core Gigabit Ethernet core port 0 45*4882a593Smuzhiyun9 gbe-bm Gigabit Ethernet Buffer Manager 46*4882a593Smuzhiyun10 sdio SDIO 47*4882a593Smuzhiyun11 usb32-sub2-sys USB 2 clock 48*4882a593Smuzhiyun12 usb32-ss-sys USB 3 clock 49*4882a593Smuzhiyun13 pcie PCIe controller 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunRequired properties: 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun- compatible : shall be "marvell,armada-3700-periph-clock-nb" for the 54*4882a593Smuzhiyun north bridge block, or 55*4882a593Smuzhiyun "marvell,armada-3700-periph-clock-sb" for the south bridge block 56*4882a593Smuzhiyun- reg : must be the register address of North/South Bridge Clock register 57*4882a593Smuzhiyun- #clock-cells : from common clock binding; shall be set to 1 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun- clocks : list of the parent clock phandle in the following order: 60*4882a593Smuzhiyun TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock. 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunExample: 64*4882a593Smuzhiyun 65*4882a593Smuzhiyunnb_perih_clk: nb-periph-clk@13000{ 66*4882a593Smuzhiyun compatible = "marvell,armada-3700-periph-clock-nb"; 67*4882a593Smuzhiyun reg = <0x13000 0x1000>; 68*4882a593Smuzhiyun clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 69*4882a593Smuzhiyun <&tbg 3>, <&xtalclk>; 70*4882a593Smuzhiyun #clock-cells = <1>; 71*4882a593Smuzhiyun}; 72