1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * 4 * (C) COPYRIGHT 2013-2023 ARM Limited. All rights reserved. 5 * 6 * This program is free software and is provided to you under the terms of the 7 * GNU General Public License version 2 as published by the Free Software 8 * Foundation, and any use by you of this program is subject to the terms 9 * of such GNU license. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, you can access it online at 18 * http://www.gnu.org/licenses/gpl-2.0.html. 19 * 20 */ 21 22 /** 23 * DOC: Default values for configuration settings 24 * 25 */ 26 27 #ifndef _KBASE_CONFIG_DEFAULTS_H_ 28 #define _KBASE_CONFIG_DEFAULTS_H_ 29 30 /* Include mandatory definitions per platform */ 31 #include <mali_kbase_config_platform.h> 32 33 enum { 34 /* Use unrestricted Address ID width on the AXI bus. */ 35 KBASE_AID_32 = 0x0, 36 37 /* Restrict GPU to a half of maximum Address ID count. 38 * This will reduce performance, but reduce bus load due to GPU. 39 */ 40 KBASE_AID_16 = 0x3, 41 42 /* Restrict GPU to a quarter of maximum Address ID count. 43 * This will reduce performance, but reduce bus load due to GPU. 44 */ 45 KBASE_AID_8 = 0x2, 46 47 /* Restrict GPU to an eighth of maximum Address ID count. 48 * This will reduce performance, but reduce bus load due to GPU. 49 */ 50 KBASE_AID_4 = 0x1 51 }; 52 53 enum { 54 /* Use unrestricted Address ID width on the AXI bus. 55 * Restricting ID width will reduce performance & bus load due to GPU. 56 */ 57 KBASE_3BIT_AID_32 = 0x0, 58 59 /* Restrict GPU to 7/8 of maximum Address ID count. */ 60 KBASE_3BIT_AID_28 = 0x1, 61 62 /* Restrict GPU to 3/4 of maximum Address ID count. */ 63 KBASE_3BIT_AID_24 = 0x2, 64 65 /* Restrict GPU to 5/8 of maximum Address ID count. */ 66 KBASE_3BIT_AID_20 = 0x3, 67 68 /* Restrict GPU to 1/2 of maximum Address ID count. */ 69 KBASE_3BIT_AID_16 = 0x4, 70 71 /* Restrict GPU to 3/8 of maximum Address ID count. */ 72 KBASE_3BIT_AID_12 = 0x5, 73 74 /* Restrict GPU to 1/4 of maximum Address ID count. */ 75 KBASE_3BIT_AID_8 = 0x6, 76 77 /* Restrict GPU to 1/8 of maximum Address ID count. */ 78 KBASE_3BIT_AID_4 = 0x7 79 }; 80 81 #if MALI_USE_CSF 82 /* 83 * Default value for the TIMER register of the IPA Control interface, 84 * expressed in milliseconds. 85 * 86 * The chosen value is a trade off between two requirements: the IPA Control 87 * interface should sample counters with a resolution in the order of 88 * milliseconds, while keeping GPU overhead as limited as possible. 89 */ 90 #define IPA_CONTROL_TIMER_DEFAULT_VALUE_MS ((u32)10) /* 10 milliseconds */ 91 #endif /* MALI_USE_CSF */ 92 93 /* Default period for DVFS sampling (can be overridden by platform header) */ 94 #ifndef DEFAULT_PM_DVFS_PERIOD 95 #define DEFAULT_PM_DVFS_PERIOD 100 /* 100ms */ 96 #endif 97 98 /* Power Management poweroff tick granuality. This is in nanoseconds to 99 * allow HR timer support (can be overridden by platform header). 100 * 101 * On each scheduling tick, the power manager core may decide to: 102 * -# Power off one or more shader cores 103 * -# Power off the entire GPU 104 */ 105 #ifndef DEFAULT_PM_GPU_POWEROFF_TICK_NS 106 #define DEFAULT_PM_GPU_POWEROFF_TICK_NS (400000) /* 400us */ 107 #endif 108 109 /* Power Manager number of ticks before shader cores are powered off 110 * (can be overridden by platform header). 111 */ 112 #ifndef DEFAULT_PM_POWEROFF_TICK_SHADER 113 #define DEFAULT_PM_POWEROFF_TICK_SHADER (2) /* 400-800us */ 114 #endif 115 116 /* Default scheduling tick granuality (can be overridden by platform header) */ 117 #ifndef DEFAULT_JS_SCHEDULING_PERIOD_NS 118 #define DEFAULT_JS_SCHEDULING_PERIOD_NS (100000000u) /* 100ms */ 119 #endif 120 121 /* Default minimum number of scheduling ticks before jobs are soft-stopped. 122 * 123 * This defines the time-slice for a job (which may be different from that of a 124 * context) 125 */ 126 #define DEFAULT_JS_SOFT_STOP_TICKS (1) /* 100ms-200ms */ 127 128 /* Default minimum number of scheduling ticks before CL jobs are soft-stopped. */ 129 #define DEFAULT_JS_SOFT_STOP_TICKS_CL (1) /* 100ms-200ms */ 130 131 /* Default minimum number of scheduling ticks before jobs are hard-stopped */ 132 #define DEFAULT_JS_HARD_STOP_TICKS_SS (50) /* 5s */ 133 134 /* Default minimum number of scheduling ticks before CL jobs are hard-stopped. */ 135 #define DEFAULT_JS_HARD_STOP_TICKS_CL (50) /* 5s */ 136 137 /* Default minimum number of scheduling ticks before jobs are hard-stopped 138 * during dumping 139 */ 140 #define DEFAULT_JS_HARD_STOP_TICKS_DUMPING (15000) /* 1500s */ 141 142 /* Default timeout for some software jobs, after which the software event wait 143 * jobs will be cancelled. 144 */ 145 #define DEFAULT_JS_SOFT_JOB_TIMEOUT (3000) /* 3s */ 146 147 /* Default minimum number of scheduling ticks before the GPU is reset to clear a 148 * "stuck" job 149 */ 150 #define DEFAULT_JS_RESET_TICKS_SS (55) /* 5.5s */ 151 152 /* Default minimum number of scheduling ticks before the GPU is reset to clear a 153 * "stuck" CL job. 154 */ 155 #define DEFAULT_JS_RESET_TICKS_CL (55) /* 5.5s */ 156 157 /* Default minimum number of scheduling ticks before the GPU is reset to clear a 158 * "stuck" job during dumping. 159 */ 160 #define DEFAULT_JS_RESET_TICKS_DUMPING (15020) /* 1502s */ 161 162 /* Nominal reference frequency that was used to obtain all following 163 * <...>_TIMEOUT_CYCLES macros, in kHz. 164 * 165 * Timeouts are scaled based on the relation between this value and the lowest 166 * GPU clock frequency. 167 */ 168 #define DEFAULT_REF_TIMEOUT_FREQ_KHZ (100000) 169 170 #if MALI_USE_CSF 171 /* Waiting timeout for status change acknowledgment, in clock cycles. 172 * 173 * This is also the default timeout to be used when an invalid timeout 174 * selector is used to retrieve the timeout on CSF GPUs. 175 * 176 * Based on 75000ms timeout at nominal 100MHz, as is required for Android - based 177 * on scaling from a 50MHz GPU system. 178 */ 179 #define CSF_FIRMWARE_TIMEOUT_CYCLES (7500000000ull) 180 181 /* Timeout in clock cycles for GPU Power Management to reach the desired 182 * Shader, L2 and MCU state. 183 * 184 * Based on 2500ms timeout at nominal 100MHz, scaled from a 50MHz GPU system. 185 */ 186 #define CSF_PM_TIMEOUT_CYCLES (250000000) 187 188 /* Waiting timeout in clock cycles for GPU reset to complete. 189 * 190 * Based on 2500ms timeout at 100MHz, scaled from a 50MHz GPU system 191 */ 192 #define CSF_GPU_RESET_TIMEOUT_CYCLES (250000000) 193 194 /* Waiting timeout in clock cycles for all active CSGs to be suspended. 195 * 196 * Based on 1500ms timeout at 100MHz, scaled from a 50MHz GPU system. 197 */ 198 #define CSF_CSG_SUSPEND_TIMEOUT_CYCLES (150000000) 199 200 /* Waiting timeout in clock cycles for GPU firmware to boot. 201 * 202 * Based on 250ms timeout at 100MHz, scaled from a 50MHz GPU system. 203 */ 204 #define CSF_FIRMWARE_BOOT_TIMEOUT_CYCLES (25000000) 205 206 /* Waiting timeout for a ping request to be acknowledged, in clock cycles. 207 * 208 * Based on 6000ms timeout at 100MHz, scaled from a 50MHz GPU system. 209 */ 210 #define CSF_FIRMWARE_PING_TIMEOUT_CYCLES (600000000ull) 211 212 #else /* MALI_USE_CSF */ 213 214 /* A default timeout in clock cycles to be used when an invalid timeout 215 * selector is used to retrieve the timeout, on JM GPUs. 216 */ 217 #define JM_DEFAULT_TIMEOUT_CYCLES (150000000) 218 219 /* Default number of milliseconds given for other jobs on the GPU to be 220 * soft-stopped when the GPU needs to be reset. 221 */ 222 #define JM_DEFAULT_RESET_TIMEOUT_MS (1) /* 1 ms */ 223 224 /* Default timeout in clock cycles to be used when checking if JS_COMMAND_NEXT 225 * is updated on HW side so a Job Slot is considered free. 226 * This timeout will only take effect on GPUs with low value for the minimum 227 * GPU clock frequency (<= 100MHz). 228 * 229 * Based on 1ms timeout at 100MHz. Will default to 0ms on GPUs with higher 230 * value for minimum GPU clock frequency. 231 */ 232 #define JM_DEFAULT_JS_FREE_TIMEOUT_CYCLES (100000) 233 234 #endif /* MALI_USE_CSF */ 235 236 /* Default timeslice that a context is scheduled in for, in nanoseconds. 237 * 238 * When a context has used up this amount of time across its jobs, it is 239 * scheduled out to let another run. 240 * 241 * @note the resolution is nanoseconds (ns) here, because that's the format 242 * often used by the OS. 243 */ 244 #define DEFAULT_JS_CTX_TIMESLICE_NS (50000000) /* 50ms */ 245 246 /* Maximum frequency (in kHz) that the GPU can be clocked. For some platforms 247 * this isn't available, so we simply define a dummy value here. If devfreq 248 * is enabled the value will be read from there, otherwise this should be 249 * overridden by defining GPU_FREQ_KHZ_MAX in the platform file. 250 */ 251 #define DEFAULT_GPU_FREQ_KHZ_MAX (5000) 252 253 /* Default timeout for task execution on an endpoint 254 * 255 * Number of GPU clock cycles before the driver terminates a task that is 256 * making no forward progress on an endpoint (e.g. shader core). 257 * Value chosen is equivalent to the time after which a job is hard stopped 258 * which is 5 seconds (assuming the GPU is usually clocked at ~500 MHZ). 259 */ 260 #define DEFAULT_PROGRESS_TIMEOUT ((u64)5 * 500 * 1024 * 1024) 261 262 /* Default threshold at which to switch to incremental rendering 263 * 264 * Fraction of the maximum size of an allocation that grows on GPU page fault 265 * that can be used up before the driver switches to incremental rendering, 266 * in 256ths. 0 means disable incremental rendering. 267 */ 268 #define DEFAULT_IR_THRESHOLD (192) 269 270 /* Waiting time in clock cycles for the completion of a MMU operation. 271 * 272 * Ideally 1.6M GPU cycles required for the L2 cache (512KiB slice) flush. 273 * 274 * As a pessimistic value, 50M GPU cycles ( > 30 times bigger ) is chosen. 275 * It corresponds to 0.5s in GPU @ 100Mhz. 276 */ 277 #define MMU_AS_INACTIVE_WAIT_TIMEOUT_CYCLES ((u64)50 * 1024 * 1024) 278 #endif /* _KBASE_CONFIG_DEFAULTS_H_ */ 279