1*4882a593Smuzhiyunfunction 1: modify ddr.bin file from ddrbin_param.txt. 2*4882a593Smuzhiyun 1) modify 'ddrbin_param.txt', set ddr frequency, uart info etc what you want. 3*4882a593Smuzhiyun If want to keep items default, please keep these items blank. 4*4882a593Smuzhiyun 2) run 'ddrbin_tool' with argument 1: ddrbin_param.txt, argument 2: ddr bin file. 5*4882a593Smuzhiyun like: ./ddrbin_tool ddrbin_param.txt px30_ddr_333MHz_v1.13.bin 6*4882a593Smuzhiyun 7*4882a593Smuzhiyunfunction 2: get ddr.bin file config to gen_param.txt file 8*4882a593Smuzhiyun If want to get ddrbin file config, please run like that: 9*4882a593Smuzhiyun ./ddrbin_tool -g gen_param.txt px30_ddr_333MHz_v1.15.bin 10*4882a593Smuzhiyun The config will show in gen_param.txt. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunThe detail information as following: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun* support ddrbin version 15*4882a593Smuzhiyun The 'X' means not support change those parameters by tool. 16*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 17*4882a593Smuzhiyun | platform | uart info | ddr freq | ssmod | DDR 2T | sr pd | drv, odt, Vref etc| dis print training info | dis CBT | 18*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 19*4882a593Smuzhiyun | RV1108 | V1.08 | V1.08 | V1.10 | V1.08 | V1.08 | X | X | X | 20*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 21*4882a593Smuzhiyun | PX30/RK3326 | V1.11 | X | V1.16 | V1.12 | V1.15 | X | X | X | 22*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 23*4882a593Smuzhiyun | RK1808 | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | 24*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 25*4882a593Smuzhiyun | RK322x | V1.08 | V1.08 | X | V1.09 | X | X | X | X | 26*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 27*4882a593Smuzhiyun | RK322xh | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | 28*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 29*4882a593Smuzhiyun | RK3288 | V1.11 | X | X | V1.11 | X | X | X | X | 30*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 31*4882a593Smuzhiyun | RK3308 | V1.28 | V1.28 | V1.31 | V1.29 | V1.30 | X | X | X | 32*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 33*4882a593Smuzhiyun | RK3308S | V2.05 | V2.05 | V2.05 | V2.05 | V2.05 | X | X | X | 34*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 35*4882a593Smuzhiyun | RK3368 | V2.04 | V2.04 | X | V2.05 | X | X | X | X | 36*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 37*4882a593Smuzhiyun | RK3328 | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | 38*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 39*4882a593Smuzhiyun | RK3399 | V1.25 | X | V1.25 | X | X | X | X | X | 40*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 41*4882a593Smuzhiyun | RK3399PRO NPU | V1.03 | V1.03 | X | V1.03 | X | X | X | X | 42*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 43*4882a593Smuzhiyun | RV1126/RV1109 | V1.00 | V1.00 | V1.05 | V1.00 | V1.05 | V1.05 | X | X | 44*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 45*4882a593Smuzhiyun | RK3566/RK3568 | V1.00 | V1.00 | V1.06 | V1.00 | V1.00 | V1.06 | V1.07 | X | 46*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 47*4882a593Smuzhiyun | RK3588 | V1.00 | V1.00 | X | V1.00 | V1.00 | V1.00 | X | X | 48*4882a593Smuzhiyun +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun| function | platform and ddrbin version | 51*4882a593Smuzhiyun| ------------------------------- | -------------------------------------- | 52*4882a593Smuzhiyun| first scan channel/channel mask | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 53*4882a593Smuzhiyun| stride type | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 54*4882a593Smuzhiyun| ext_temp_ref | Null | 55*4882a593Smuzhiyun| link_ecc_en | Null | 56*4882a593Smuzhiyun| per_bank_ref_en | RK3588 V1.09 | 57*4882a593Smuzhiyun| derate_en | RK3588 V1.09 | 58*4882a593Smuzhiyun| auto_precharge_en | Null | 59*4882a593Smuzhiyun| res_space_remap_portion | RK3588 V1.09 | 60*4882a593Smuzhiyun| res_space_remap_all | RK3588 V1.09 | 61*4882a593Smuzhiyun| rd_vref_scan_en | RK3588 V1.08 | 62*4882a593Smuzhiyun| wr_vref_scan_en | RK3588 V1.08 | 63*4882a593Smuzhiyun| eye_2d_scan_en | RK3588 V1.08 | 64*4882a593Smuzhiyun| ch/bank/rank_mask | RK3588 V1.00 | 65*4882a593Smuzhiyun| pstore base_addr/buf_size | RK3588 V1.09 | 66*4882a593Smuzhiyun| uboot/atf/optee/spl/tpl log en | RK3588 V1.09 | 67*4882a593Smuzhiyun| boot_fsp | RK3588 V1.09 | 68*4882a593Smuzhiyun| pageclose | RK3588 V1.10 | 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun* UART info 71*4882a593Smuzhiyun 72*4882a593Smuzhiyunuart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart. 73*4882a593Smuzhiyunuart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2), 74*4882a593Smuzhiyunor 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c). 75*4882a593Smuzhiyunuart baudrate: uart baudrate should be 115200 or 1500000. 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun* disable print training information 78*4882a593Smuzhiyun 79*4882a593Smuzhiyundis_train_print: 1: will disabled print training information; 0: will enable print training information. 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun* recycle registers space(remap register space to DDR) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyunres_space_remap_portion 84*4882a593Smuzhiyun1: will remap the part of registers to DDR memory space(will not larger than 4GB). 85*4882a593SmuzhiyunIt is PCIE and some reserved space in RK3588, and the PCIE can not be used when set to 1. 86*4882a593Smuzhiyun 87*4882a593Smuzhiyunres_space_remap_all 88*4882a593Smuzhiyun1: will wrap all registers space(include res_space_remap_portion enable space) to DDR memory space. This space would be place in larger than 4GB. 89*4882a593SmuzhiyunThe PCIE can be used when set to 1 in RK3588. 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun* DDR eye scanning 92*4882a593Smuzhiyun1) eye_2d_scan_en: 1: will enable 2D eye scanning for debug purpose, vref and skew eye scanning. 93*4882a593Smuzhiyun2) wr_vref_scan_en: 1: enable vref scan and use scanning result for write. 94*4882a593Smuzhiyun3) rd_vref_scan_en: 1: enable vref scan and use scanning result for read. 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun* DDR auto precharge 97*4882a593Smuzhiyun 98*4882a593Smuzhiyunauto_precharge_en: 1: will enable the DDR auto precharge. 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun* DDR refresh derate 101*4882a593Smuzhiyun 102*4882a593Smuzhiyunderate_en: 1: will enable derate function of the LP2/LP3/LP4/LP4X/LP5. 103*4882a593SmuzhiyunThe high temperature will issue more refresh command and the low temperature will less. 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun* DDR per bank refresh 106*4882a593Smuzhiyun 107*4882a593Smuzhiyunper_bank_ref_en: 1: will enable per bank refresh 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun* link ECC enable 110*4882a593Smuzhiyun 111*4882a593Smuzhiyunlink_ecc_en: 1: read/write link ecc enable. 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun* Extended temperature refresh 114*4882a593Smuzhiyun 115*4882a593Smuzhiyunext_temp_ref: 116*4882a593Smuzhiyun 0: ref1x for normal chip, 2x for 3568M/3568J 117*4882a593Smuzhiyun 1: fix 2x ref for all chip 118*4882a593Smuzhiyun 2: fix 4x ref for all chip 119*4882a593Smuzhiyun 3: fix 1x ref for all chip 120*4882a593SmuzhiyunNote: If derate-enabled DDR are configured with derate_en=1, the ext_temp_ref configuration does not take effect. 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun* pstore_base_addr pstore_buf_size 123*4882a593SmuzhiyunThe pstore buffer base address: pstore_base_addr << 16, 64kB align. 124*4882a593SmuzhiyunThe pstore buffer size: pstore_buf_size * 4KB. 125*4882a593SmuzhiyunIt is define the addr and size to save ddrbin log for last log. 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun* uboot_log_en 128*4882a593Smuzhiyun1: enable uboot log. 129*4882a593Smuzhiyun0: disable uboot log. 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun* atf_log_en 132*4882a593Smuzhiyun1: enable atf log. 133*4882a593Smuzhiyun0: disable atf log. 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun* optee_log_en 136*4882a593Smuzhiyun1: enable optee log. 137*4882a593Smuzhiyun0: disable optee log. 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun* spl_log_en 140*4882a593Smuzhiyun1: enable spl log. 141*4882a593Smuzhiyun0: disable spl log. 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun* tpl_log_en 144*4882a593Smuzhiyun1: enable tpl log. 145*4882a593Smuzhiyun0: disable tpl log. 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun* pageclose 148*4882a593Smuzhiyun1: enable pageclose. 149*4882a593Smuzhiyun0: disable pageclose. 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun* boot_fsp 152*4882a593SmuzhiyunTo choose the which DDR freq to boot system. 0 means fsp0_freq, 1 means fsp1_freq, 2 means fsp2_freq, 3 means fsp3_freq, the default is 0. 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun* DDR (final) freq(also called ddrx_f0_freq_mhz/fsp0_freq) 155*4882a593Smuzhiyun 156*4882a593SmuzhiyunFor RK3588, the boot_fsp used to choose which ddrx_fx_freq_mhz/fspx_freq to boot system, default is ddrx_f0_freq_mhz/fsp0_freq. 157*4882a593SmuzhiyunFor the others platform, it is the final freq to boot system. 158*4882a593Smuzhiyun 159*4882a593Smuzhiyunddr2_freq(ddr2_f0_freq_mhz): ddr2 frequency, unit:MHz. 160*4882a593Smuzhiyunlp2_freq (lp2_f0_freq_mhz): lpddr2 frequency, unit:MHz. 161*4882a593Smuzhiyunddr3_freq(ddr3_f0_freq_mhz): ddr3 frequency, unit:MHz. 162*4882a593Smuzhiyunlp3_freq (lp3_f0_freq_mhz): lpddr3 frequency, unit:MHz. 163*4882a593Smuzhiyunddr4_freq(ddr4_f0_freq_mhz): ddr4 frequency, unit:MHz. 164*4882a593Smuzhiyunlp4_freq (lp4_f0_freq_mhz): lpddr4 frequency, unit:MHz. 165*4882a593Smuzhiyunlp4x_freq(lp4x_f0_freq_mhz): lpddr4x frequency, unit:MHz. 166*4882a593Smuzhiyunlp5_freq (lp5_f0_freq_mhz): lpddr5 frequency, unit:MHz. 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun* support ddr frequency: 169*4882a593SmuzhiyunThe 'X' as follows means not support change frequencies by tool. 170*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 171*4882a593Smuzhiyun| platform | support frequencies(MHZ) | 172*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 173*4882a593Smuzhiyun| RK1108 | DDR2: 400; LP2: <= 533; DDR3: <= 800 | 174*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 175*4882a593Smuzhiyun| PX30/RK3326 | X | 176*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 177*4882a593Smuzhiyun| RK1808 | 333,400,533,666,786,933 | 178*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 179*4882a593Smuzhiyun| RK322x | DDR2/LP2: <= 533; others: <= 800 | 180*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 181*4882a593Smuzhiyun| RK322xh | X | 182*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 183*4882a593Smuzhiyun| RK3288 | X | 184*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 185*4882a593Smuzhiyun| RK3308/RK3308S| DDR2/LP2: 393,451; DDR3: 393,451,589 | 186*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 187*4882a593Smuzhiyun| RK3368 | DDR3: <= 800; LP3: <= 666 | 188*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 189*4882a593Smuzhiyun| RK3328 | X | 190*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 191*4882a593Smuzhiyun| RK3399 | X | 192*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 193*4882a593Smuzhiyun| RK3399PRO NPU | 333,400,533,666,786,933 | 194*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 195*4882a593Smuzhiyun| RV1126/RV1109 | 328,396,528,664,784,924,1056 | 196*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 197*4882a593Smuzhiyun| RK3566 | 324,396,528,630,780,920,1056 | 198*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 199*4882a593Smuzhiyun| RK3568 | DDR3/LP3: 324,396,528,630,780,920,1056 | 200*4882a593Smuzhiyun| | DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184,1332,1560 | 201*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 202*4882a593Smuzhiyun| RK3588 | LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz] | 203*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 204*4882a593Smuzhiyun| RK3528 | DDR3/LP3: 324,396,528,630,780,920,1056 | 205*4882a593Smuzhiyun| | DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184 | 206*4882a593Smuzhiyun+---------------+-----------------------------------------------------------------+ 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun* DDR frequencies(add more) 209*4882a593Smuzhiyun 210*4882a593Smuzhiyunddr2_f1_freq_mhz: ddr2 frequency fsp 1, unit:MHz. 211*4882a593Smuzhiyunddr2_f2_freq_mhz: ddr2 frequency fsp 2, unit:MHz. 212*4882a593Smuzhiyunddr2_f3_freq_mhz: ddr2 frequency fsp 3, unit:MHz. 213*4882a593Smuzhiyunddr2_f4_freq_mhz: ddr2 frequency fsp 4, unit:MHz. 214*4882a593Smuzhiyunddr2_f5_freq_mhz: ddr2 frequency fsp 5, unit:MHz. 215*4882a593Smuzhiyun... 216*4882a593SmuzhiyunThe ddrx_f0_freq_mhz(the fsp0 frequency) is named ddrx_freq. 217*4882a593Smuzhiyun 218*4882a593Smuzhiyunddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568, RK3588 used. 219*4882a593SmuzhiyunThe program will initialize dram by following order. 220*4882a593Smuzhiyunfor example: ddr4_f1_freq_mhz --> ddr4_f2_freq_mhz --> ddr4_f3_freq_mhz --> ddr4_freq. 221*4882a593SmuzhiyunAnd the final frequency is ddr4_freq to boot system. 222*4882a593SmuzhiyunThe ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 223*4882a593SmuzhiyunSo it is better to arrange the frequency values in order as above. That means the max freq is in final freq(lp*/ddr*_freq) and the min freq is in 'ddr*/lp*_f1_freq_mhz'. 224*4882a593SmuzhiyunSuch as: ddr*/lp*_f1_freq_mhz < ddr*/lp*_f2_freq_mhz < ddr*/lp*_f3_freq_mhz < lp*/ddr*_freq(the final freq) 225*4882a593SmuzhiyunFor example: 226*4882a593Smuzhiyun ... 227*4882a593Smuzhiyun ddr4_freq=1560 228*4882a593Smuzhiyun ... 229*4882a593Smuzhiyun ddr4_f1_freq_mhz=324 230*4882a593Smuzhiyun ddr4_f2_freq_mhz=528 231*4882a593Smuzhiyun ddr4_f3_freq_mhz=780 232*4882a593Smuzhiyun ... 233*4882a593Smuzhiyun 234*4882a593SmuzhiyunNote: The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun* SR PD idle 237*4882a593Smuzhiyun 238*4882a593Smuzhiyunsr_idle: auto self-refresh mode delay time. 239*4882a593Smuzhiyunpd_idle: auto power-down mode delay time. 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun* DDR 2T 242*4882a593Smuzhiyun 243*4882a593Smuzhiyunddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T. 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun* PLL ssmod 246*4882a593Smuzhiyun 247*4882a593SmuzhiyunThese parameters are about Spread Spectrum Modulator(ssmod) for PLL. 248*4882a593Smuzhiyunssmod_downspread: ssmod work mode. 1: down spread, 0: center spread. 249*4882a593Smuzhiyunssmod_div: Divider required to set the modulation frequency. RK3308 suggests to ssmod_div=2, others platforms suggest to ssmod_div=5. 250*4882a593Smuzhiyunssmod_spread: spread amplitude % = 0.1 * ssmod_spread; 0: disable ssmod, others will enable ssmod, max to 0x1f. 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun* driver strength 253*4882a593Smuzhiyun 254*4882a593Smuzhiyunphy_ddr*_dq_drv_when_odten_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt on. unit: ohm. 255*4882a593Smuzhiyunphy_ddr*_ca_drv_when_odten_ohm: The PHY CMD/ADDR driver strength when DRAM odt on. unit: ohm. 256*4882a593Smuzhiyunphy_ddr*_clk_drv_when_odten_ohm: The PHY clock driver strength when DRAM odt on. unit: ohm. 257*4882a593Smuzhiyunddr*_dq_drv_when_odten_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt on. unit: ohm. 258*4882a593Smuzhiyunphy_ddr*_dq_drv_when_odtoff_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt off. unit: ohm. 259*4882a593Smuzhiyunphy_ddr*_ca_drv_when_odtoff_ohm: The PHY CMD/ADDR driver strength when DRAM odt off. unit: ohm. 260*4882a593Smuzhiyunphy_ddr*_clk_drv_when_odtoff_ohm: The PHY clock driver strength when DRAM odt off. unit: ohm. 261*4882a593Smuzhiyunddr*_dq_drv_when_odtoff_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt off. unit: ohm. 262*4882a593Smuzhiyun 263*4882a593SmuzhiyunThe phy side driver strength support value as follows: 264*4882a593Smuzhiyun+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 265*4882a593Smuzhiyun| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 266*4882a593Smuzhiyun+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 267*4882a593Smuzhiyun| | 455,230,153,115, | 482,244,162,122, | | 501,253,168,126,| | | | 268*4882a593Smuzhiyun| | 91,76,65,57,51,46,| 97,81,69,61,54,48,| | 101,84,72,63,56,| | | | 269*4882a593Smuzhiyun| RV1126/RV1109 | 41,38,35,32,30,28,| 44,40,37,34,32,30,| follow DDR4 | 50,46,42,38,36, | follow LP4 | follow LP4 | X | 270*4882a593Smuzhiyun| | 27,25,24,23,22,21,| 28,27,25,24,23,22,| | 33,31,29,28,26, | | | | 271*4882a593Smuzhiyun| | 20 | 21 | | 25,24,23,22 | | | | 272*4882a593Smuzhiyun+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 273*4882a593Smuzhiyun| | 500,250,167,125, | 556,279,185,139, | | 576,289,192,144,| 646,323,215, | 513,259,172, | | 274*4882a593Smuzhiyun| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64,| 162,129,108,92,| 130,104,86,74, | | 275*4882a593Smuzhiyun| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37,| follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 276*4882a593Smuzhiyun| | 31,29,28,26,25,24,| 34,32,31,29,27,26,| | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 277*4882a593Smuzhiyun| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 278*4882a593Smuzhiyun| | | | | | 28 | 23 | | 279*4882a593Smuzhiyun+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 280*4882a593Smuzhiyun| RK3588 | X | X | X | 240,120,80,60, | follow LP4 | follow LP4 | follow LP4 | 281*4882a593Smuzhiyun| | | | | 48,40,34,30 | | | | 282*4882a593Smuzhiyun+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 283*4882a593Smuzhiyun| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165,| 585,297,202, | 585,297,202, | | 284*4882a593Smuzhiyun| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74,| 150,122,103,90,| 150,122,103,90,| | 285*4882a593Smuzhiyun| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43,| follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 286*4882a593Smuzhiyun| | 38,36,34,33,31,30,| 39,37,35,34,32,31,| | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 287*4882a593Smuzhiyun| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 288*4882a593Smuzhiyun| | | | | | 30 | 30 | | 289*4882a593Smuzhiyun+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 290*4882a593Smuzhiyun 291*4882a593SmuzhiyunThe DRAM side driver strength support value as follows: 292*4882a593Smuzhiyun+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 293*4882a593Smuzhiyun| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X | LP5 | 294*4882a593Smuzhiyun+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 295*4882a593Smuzhiyun| all | 40,34 | 34,48 | 34,40,48,60,80 | 40,48,60,80,120,240 | follow LP4 | follow LP4 | 296*4882a593Smuzhiyun+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun* ODT 299*4882a593Smuzhiyunphy_ddr*_odt_ohm: The PHY ODT strength(read direction). unit: ohm. 300*4882a593Smuzhiyunddr*_odt_ohm: The DRAM ODT strength(write direction). unit: ohm. 301*4882a593Smuzhiyunphy_ddr*_odt_pull_up_en: 1: enable PHY pull up odt. 0: disable 302*4882a593Smuzhiyunphy_ddr*_odt_pull_dn_en: 1: enable PHY pull down odt. 0: disable 303*4882a593Smuzhiyunphy_ddr*_odten_freq_mhz: The PHY odt enable when larger than this frequency. unit: MHz. 304*4882a593Smuzhiyunddr*_odten_freq_mhz: The DRAM odt(DQ/DQS) enable when larger than this frequency. unit: MHz. 305*4882a593Smuzhiyun 306*4882a593SmuzhiyunThe phy side ODT support value as follows: 307*4882a593SmuzhiyunThe ODT "0" means disabled ODT. 308*4882a593Smuzhiyun+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 309*4882a593Smuzhiyun| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 310*4882a593Smuzhiyun+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 311*4882a593Smuzhiyun| | 0,561,282,188,141,| 0,586,294,196,148, | | 0,604,303,202,152,| | | | 312*4882a593Smuzhiyun| | 113,94,81,72,64, | 118,99,58,76,67,60,| | 122,101,87,78,69, | | | | 313*4882a593Smuzhiyun| RV1126/RV1109 | 58,52,48,44,41, | 55,50,46,43,40,38, | follow DDR4 | 62,56,52,48,44,41,| follow LP4 | follow LP4 | X | 314*4882a593Smuzhiyun| | 38,37,34,32,31,29,| 36,34,32,31,29,28, | | 39,37,35,33,32,30,| | | | 315*4882a593Smuzhiyun| | 28,27,25 | 27 | | 29,27 | | | | 316*4882a593Smuzhiyun+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 317*4882a593Smuzhiyun| | 0,500,250,167,125,| 0,556,279,185,139, | | 0,576,289,192,144,| 0,646,323,215, | 0,513,259,172, | | 318*4882a593Smuzhiyun| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64, | 162,129,108,92,| 130,104,86,74, | | 319*4882a593Smuzhiyun| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37, | follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 320*4882a593Smuzhiyun| | 31,29,28,26,25,24,| 34,32,31,29,27,26, | | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 321*4882a593Smuzhiyun| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 322*4882a593Smuzhiyun| | | | | | 28 | 23 | | 323*4882a593Smuzhiyun+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 324*4882a593Smuzhiyun| RK3588 | X | X | X | 0,240,120,80, | follow LP4 | follow LP4 | follow LP4 | 325*4882a593Smuzhiyun| | | | | 60,48,40,34,30 | | | | 326*4882a593Smuzhiyun+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 327*4882a593Smuzhiyun| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165, | 585,297,202, | 585,297,202, | | 328*4882a593Smuzhiyun| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74, | 150,122,103,90,| 150,122,103,90,| | 329*4882a593Smuzhiyun| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43, | follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 330*4882a593Smuzhiyun| | 38,36,34,33,31,30,| 39,37,35,34,32,31, | | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 331*4882a593Smuzhiyun| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 332*4882a593Smuzhiyun| | | | | | 30 | 30 | | 333*4882a593Smuzhiyun+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 334*4882a593SmuzhiyunThe DRAM side ODT support value as follows: 335*4882a593Smuzhiyun+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 336*4882a593Smuzhiyun| platform | DDR3 | DDR4 | LP3 | LP4(include DQ and CA)| LP4X | LP5 | 337*4882a593Smuzhiyun+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 338*4882a593Smuzhiyun| all | 0,40,60,120 | 0,34,40,48,60,120 | 0,60,120,240 | 0,40,48,60,80,120,240 | follow LP4 | follow LP4 | 339*4882a593Smuzhiyun+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun* slew rate 342*4882a593Smuzhiyun 343*4882a593Smuzhiyunphy_ddr*_dq_sr_when_odten: The PHY DQ/DQS slew rate when odt on. 344*4882a593Smuzhiyunphy_ddr*_ca_sr_when_odten: The PHY CMD/ADDR slew rate when odt on. 345*4882a593Smuzhiyunphy_ddr*_clk_sr_when_odten: The PHY clock slew rate when odt on. 346*4882a593Smuzhiyunphy_ddr*_dq_sr_when_odtoff: The PHY DQ/DQS slew rate when odt off. 347*4882a593Smuzhiyunphy_ddr*_ca_sr_when_odtoff: The PHY CMD/ADDR slew rate when odt off. 348*4882a593Smuzhiyunphy_ddr*_clk_sr_when_odtoff: The PHY clock slew rate when odt off. 349*4882a593Smuzhiyun 350*4882a593SmuzhiyunThe max value is 0x1f, the min is 0x0. 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun* byte map 353*4882a593Smuzhiyun 354*4882a593Smuzhiyunddr*_bytes_map: The bytes remap in PHY. 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun* dq remap 357*4882a593Smuzhiyun 358*4882a593Smuzhiyunlp*_dq*_*_map: The dq remap in PHY. 359*4882a593Smuzhiyunddr*_cs*_dq*_dq*_map: The dq remap in PHY. 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun* lp4/lp4x more information 362*4882a593Smuzhiyun 363*4882a593Smuzhiyunlp4*_ca_odten_freq_mhz: The DRAM CMD/ADDR odt enable when larger than this frequency. unit: MHz. 364*4882a593Smuzhiyunphy_lp4*_dq_vref_when_odten: The PHY VrefDQ when PHY odt on. uint: parts per thousand. 365*4882a593Smuzhiyunlp4*_dq_vref_when_odten: The DRAM VrefDQ when DRAM DQ/DQS odt on. uint: parts per thousand. 366*4882a593Smuzhiyunlp4*_ca_vref_when_odten: The DRAM VrefCA when DRAM CA odt on. uint: parts per thousand. 367*4882a593Smuzhiyunphy_lp4_dq_vref_when_odtoff: The PHY VrefDQ when PHY odt off. uint: parts per thousand. 368*4882a593Smuzhiyunlp4_dq_vref_when_odtoff: The DRAM VrefDQ when DRAM DQ/DQS odt off. uint: parts per thousand. 369*4882a593Smuzhiyunlp4_ca_vref_when_odtoff: The DRAM VrefCA when DRAM CA odt off. uint: parts per thousand. 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun* hash info 372*4882a593Smuzhiyunch/bank/rank_mask*: is used to DDR address hash mask. 373