Lines Matching +full:50 +full:mhz

16  * refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
70  * refclk_freq - input reference clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
192 	/* setup the sys clock divider for CORE_CLK (1000MHz) */  in setup_sys_clocks()
196 	/* setup the sys clock divider for CORE2_CLK (500MHz) */  in setup_sys_clocks()
199 	/* setup the sys clock divider for SYS3_CLK (266 MHz) */  in setup_sys_clocks()
203 	/* setup the sys clock divider for SYS6_CLK (133 Mhz) */  in setup_sys_clocks()
215 	 * (source: PERIPH_PLL_PHI_0/5, PERI_CLK - 80 MHz)  in setup_aux_clocks()
220 	/* setup the aux clock divider for LIN_CLK (40MHz) */  in setup_aux_clocks()
224 	/* setup the aux clock divider for ENET_TIME_CLK (50MHz) */  in setup_aux_clocks()
228 	/* setup the aux clock divider for ENET_CLK (50MHz) */  in setup_aux_clocks()
232 	/* setup the aux clock divider for SDHC_CLK (50 MHz). */  in setup_aux_clocks()
236 	/* setup the aux clock divider for DDR_CLK (533MHz) and APEX_SYS_CLK (266MHz) */  in setup_aux_clocks()
239 	/* setup the aux clock divider for DDR4_CLK (133,25MHz) */  in setup_aux_clocks()