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/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c33 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
35 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
36 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
37 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
39 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
44 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
45 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
46 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-s3c2410.c62 { .val = 1, .div = 2 },
63 { .val = 2, .div = 4 },
123 PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
124 PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
125 PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
126 PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
127 PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
129 PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
130 PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
131 PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
[all …]
H A Dclk-exynos3250.c99 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
228 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
229 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
344 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
455 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
497 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
508 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
536 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
547 GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
564 GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/spear/
H A Dspear1340_clock.c10 * License version 2. This program is licensed "as is" without any
34 #define SPEAR1340_GEN_SYNT_CLK_MASK 2
36 #define SPEAR1340_PLL_CLK_MASK 2
59 #define SPEAR1340_UART_CLK_MASK 2
62 #define SPEAR1340_CLCD_CLK_MASK 2
63 #define SPEAR1340_CLCD_CLK_SHIFT 2
69 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
70 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
87 #define SPEAR1340_I2S_REF_SHIFT 2
88 #define SPEAR1340_I2S_SRC_CLK_MASK 2
[all …]
H A Dspear1310_clock.c10 * License version 2. This program is licensed "as is" without any
26 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2
28 #define SPEAR1310_RAS_SYNT_CLK_MASK 2
30 #define SPEAR1310_PLL_CLK_MASK 2
54 #define SPEAR1310_UART_CLK_SYNT_VAL 2
55 #define SPEAR1310_UART_CLK_MASK 2
60 #define SPEAR1310_CLCD_CLK_MASK 2
61 #define SPEAR1310_CLCD_CLK_SHIFT 2
70 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
87 #define SPEAR1310_I2S_REF_SHIFT 2
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h33 u32 pmucru_clkfrac_con[2];
37 u32 pmucru_softrst_con[2];
38 u32 reserved4[2];
39 u32 pmucru_rstnhold_con[2];
40 u32 reserved5[2];
41 u32 pmucru_gatedis_con[2];
47 u32 reserved[2];
49 u32 reserved1[2];
51 u32 reserved2[2];
53 u32 reserved3[2];
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Dopp2xxx.h70 #define R1_CLKSEL_L4 (2 << 5)
75 #define R1_CLKSEL_MPU (2 << 0)
77 #define R1_CLKSEL_DSP (2 << 0)
78 #define R1_CLKSEL_DSP_IF (2 << 5)
80 #define R1_CLKSEL_GFX (2 << 0)
85 /* 2430-Ratio Config 2 */
87 #define R2_CLKSEL_L4 (2 << 5)
88 #define R2_CLKSEL_USB (2 << 25)
92 #define R2_CLKSEL_MPU (2 << 0)
94 #define R2_CLKSEL_DSP (2 << 0)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c37 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
41 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
42 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
43 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
44 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
45 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
46 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
47 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
51 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
56 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/
H A Dbcmwifi_channels.c10 * under the terms of the GNU General Public License version 2 (the "GPL"),
51 /* Definitions for D11AC capable (80MHz+) Chanspec type */
56 * ['/'<1st-channel-segment>'-'<2nd-channel-segment>]]
59 * (optional) 2, 4, 5, 6 for 2.4GHz, 4GHz, 5GHz, and 6GHz respectively.
60 * Default value is 2g if channel <= 14, otherwise 5g.
62 * channel number of the 20MHz channel,
63 * or primary 20 MHz channel of 40MHz, 80MHz, 160MHz, 80+80MHz,
64 * 240MHz, 320MHz, or 160+160MHz channels.
68 * 'u' or 'l' (only for 2.4GHz band 40MHz)
70 * For 2.4GHz band 40MHz channels, the same primary channel may be the
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/
H A Dbcmwifi_channels.c10 * under the terms of the GNU General Public License version 2 (the "GPL"),
51 /* Definitions for D11AC capable (80MHz+) Chanspec type */
56 * ['/'<1st-channel-segment>'-'<2nd-channel-segment>]]
59 * (optional) 2, 4, 5, 6 for 2.4GHz, 4GHz, 5GHz, and 6GHz respectively.
60 * Default value is 2g if channel <= 14, otherwise 5g.
62 * channel number of the 20MHz channel,
63 * or primary 20 MHz channel of 40MHz, 80MHz, 160MHz, 80+80MHz,
64 * 240MHz, 320MHz, or 160+160MHz channels.
68 * 'u' or 'l' (only for 2.4GHz band 40MHz)
70 * For 2.4GHz band 40MHz channels, the same primary channel may be the
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/infineon/
H A Dbcmwifi_channels.c12 * under the terms of the GNU General Public License version 2 (the "GPL"),
59 /* Definitions for D11AC capable (80MHz+) Chanspec type */
62 * [<band> 'g'] <channel> ['/'<bandwidth> [<primary-sideband>]['/'<1st80channel>'-'<2nd80channel>]]
65 * (optional) 2, 3, 4, 5 for 2.4GHz, 3GHz, 4GHz, and 5GHz respectively.
66 * Default value is 2g if channel <= 14, otherwise 5g.
68 * channel number of the 5MHz, 10MHz, 20MHz channel,
69 * or primary channel of 40MHz, 80MHz, 160MHz, or 80+80MHz channel.
73 * (only for 2.4GHz band 40MHz) U for upper sideband primary, L for lower.
75 * For 2.4GHz band 40MHz channels, the same primary channel may be the
76 * upper sideband for one 40MHz channel, and the lower sideband for an
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/
H A Dbcmwifi_channels.c11 * under the terms of the GNU General Public License version 2 (the "GPL"),
59 * [<band> 'g'] <channel> ['/'<bandwidth> [<ctl-sideband>]['/'<1st80channel>'-'<2nd80channel>]]
62 * (optional) 2, 3, 4, 5 for 2.4GHz, 3GHz, 4GHz, and 5GHz respectively.
63 * Default value is 2g if channel <= 14, otherwise 5g.
65 * channel number of the 5MHz, 10MHz, 20MHz channel,
66 * or primary channel of 40MHz, 80MHz, 160MHz, or 80+80MHz channel.
70 * (only for 2.4GHz band 40MHz) U for upper sideband primary, L for lower.
72 * For 2.4GHz band 40MHz channels, the same primary channel may be the
73 * upper sideband for one 40MHz channel, and the lower sideband for an
74 * overlapping 40MHz channel. The U/L disambiguates which 40MHz channel
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/
H A Dbcmwifi_channels.c12 * under the terms of the GNU General Public License version 2 (the "GPL"),
59 /* Definitions for D11AC capable (80MHz+) Chanspec type */
62 * [<band> 'g'] <channel> ['/'<bandwidth> [<primary-sideband>]['/'<1st80channel>'-'<2nd80channel>]]
65 * (optional) 2, 3, 4, 5 for 2.4GHz, 3GHz, 4GHz, and 5GHz respectively.
66 * Default value is 2g if channel <= 14, otherwise 5g.
68 * channel number of the 5MHz, 10MHz, 20MHz channel,
69 * or primary channel of 40MHz, 80MHz, 160MHz, or 80+80MHz channel.
73 * (only for 2.4GHz band 40MHz) U for upper sideband primary, L for lower.
75 * For 2.4GHz band 40MHz channels, the same primary channel may be the
76 * upper sideband for one 40MHz channel, and the lower sideband for an
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/infineon/bcmdhd/
H A Dbcmwifi_channels.c12 * under the terms of the GNU General Public License version 2 (the "GPL"),
59 /* Definitions for D11AC capable (80MHz+) Chanspec type */
62 * [<band> 'g'] <channel> ['/'<bandwidth> [<primary-sideband>]['/'<1st80channel>'-'<2nd80channel>]]
65 * (optional) 2, 3, 4, 5 for 2.4GHz, 3GHz, 4GHz, and 5GHz respectively.
66 * Default value is 2g if channel <= 14, otherwise 5g.
68 * channel number of the 5MHz, 10MHz, 20MHz channel,
69 * or primary channel of 40MHz, 80MHz, 160MHz, or 80+80MHz channel.
73 * (only for 2.4GHz band 40MHz) U for upper sideband primary, L for lower.
75 * For 2.4GHz band 40MHz channels, the same primary channel may be the
76 * upper sideband for one 40MHz channel, and the lower sideband for an
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/mvebu/
H A Dmv98dx3236.c25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
97 static const int __initconst mv98dx3236_cpu_mpll_ratios[8][2] = {
102 static const int __initconst mv98dx3236_cpu_ddr_ratios[8][2] = {
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h7 static char *qla2x00_model_name[QLA_MODEL_NAMES*2] = {
8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
16 "QCP2332", "Sun cPCI to 2Gb FC, Dual Channel", /* 0x108 */
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/bsc9132qds/
H A DREADME23 ECC), up to 1333 MHz data rate
48 - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
56 2Gbyte DDR3 (on board DDR), Dual Ranki
58 128Mbyte 2K page size NAND Flash
73 Core MHz/CCB MHz/DDR(MT/s)
74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
82 2. NAND Flash
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
25 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
39 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
74 UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
83 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
84 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
85 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
86 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
90 UNIPHIER_LD4_SYS_CLK_NAND(2),
[all …]
/OK3568_Linux_fs/kernel/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
16 # 12 chars 2 lines
18 # 2 chars 10 lines
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/common/
H A Didt8t49n222a_serdes_clk.h23 SERDES_REFCLK_100, /* refclk 100Mhz */
24 SERDES_REFCLK_122_88, /* refclk 122.88Mhz */
25 SERDES_REFCLK_125, /* refclk 125Mhz */
26 SERDES_REFCLK_156_25, /* refclk 156.25Mhz */
31 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
33 static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
43 * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
45 static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
55 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
58 static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
[all …]
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3588.c26 RK3588_PLL_RATE(1500000000, 2, 250, 1, 0),
27 RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
28 RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
29 RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
30 RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
31 RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
32 RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
33 RK3588_PLL_RATE(850000000, 3, 425, 2, 0),
34 RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
35 RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/
H A Dcpu.c29 return 2; in get_num_cpus()
56 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
57 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
58 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
59 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
60 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
61 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
74 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
75 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
76 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
[all …]
/OK3568_Linux_fs/kernel/drivers/media/usb/dvb-usb-v2/
H A Daf9035.h58 u8 af9033_i2c_addr[2];
60 struct af9033_config af9033_config[2];
65 struct platform_device *platform_device_tuner[2];
81 16384000, /* 16.38 MHz */
82 20480000, /* 20.48 MHz */
83 36000000, /* 36.00 MHz */
84 30000000, /* 30.00 MHz */
85 26000000, /* 26.00 MHz */
86 28000000, /* 28.00 MHz */
87 32000000, /* 32.00 MHz */
[all …]
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3308.c43 #elif (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 2)
115 /* DPLL VPLL0 VPLL1 mode in 24MHz*/ in rkdclk_init()
131 /* set vpll1 in 903.168MHz vco = 1.806GHz */ in rkdclk_init()
132 rk3308_pll_div.refdiv = 2; in rkdclk_init()
134 rk3308_pll_div.postdiv1 = 2; in rkdclk_init()
141 /* set vpll0 in 786.432MHz vco = 3.146GHz */ in rkdclk_init()
142 rk3308_pll_div.refdiv = 2; in rkdclk_init()
149 /* set vpll0 in 1179.648MHz, vco = 2.359GHz*/ in rkdclk_init()
150 rk3308_pll_div.refdiv = 2; in rkdclk_init()
152 rk3308_pll_div.postdiv1 = 2; in rkdclk_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dphy_shim.h28 #define RADAR_TYPE_ETSI_2 2 /* ETSI 2 Radar type */
34 #define RADAR_TYPE_STG2 8 /* staggered-2 radar */
49 #define ANTSEL_2x4 1 /* 2x4 boardlevel selection available */
50 #define ANTSEL_2x3 2 /* 2x3 CB2 boardlevel selection available */
55 #define ANT_RX_DIV_START_1 2 /* Choose starting with 1 */
60 #define WL_ANT_RX_MAX 2 /* max 2 receive antennas */
63 #define WL_ANT_IDX_2 1 /* antenna index 2 */
68 #define BRCMS_N_PREAMBLE_GF_BRCM 2
80 /* Index for first 20MHz OFDM SISO rate */
82 /* Index for first 20MHz OFDM CDD rate */
[all …]

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