1*4882a593SmuzhiyunOverview 2*4882a593Smuzhiyun-------- 3*4882a593Smuzhiyun The BSC9132 is a highly integrated device that targets the evolving 4*4882a593Smuzhiyun Microcell, Picocell, and Enterprise-Femto base station market subsegments. 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 7*4882a593Smuzhiyun core technologies with MAPLE-B2P baseband acceleration processing elements 8*4882a593Smuzhiyun to address the need for a high performance, low cost, integrated solution 9*4882a593Smuzhiyun that handles all required processing layers without the need for an 10*4882a593Smuzhiyun external device except for an RF transceiver or, in a Micro base station 11*4882a593Smuzhiyun configuration, a host device that handles the L3/L4 and handover between 12*4882a593Smuzhiyun sectors. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun The BSC9132 SoC includes the following function and features: 15*4882a593Smuzhiyun - Power Architecture subsystem including two e500 processors with 16*4882a593Smuzhiyun 512-Kbyte shared L2 cache 17*4882a593Smuzhiyun - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 18*4882a593Smuzhiyun cache 19*4882a593Smuzhiyun - 32 Kbyte of shared M3 memory 20*4882a593Smuzhiyun - The Multi Accelerator Platform Engine for Pico BaseStation Baseband 21*4882a593Smuzhiyun Processing (MAPLE-B2P) 22*4882a593Smuzhiyun - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including 23*4882a593Smuzhiyun ECC), up to 1333 MHz data rate 24*4882a593Smuzhiyun - Dedicated security engine featuring trusted boot 25*4882a593Smuzhiyun - Two DMA controllers 26*4882a593Smuzhiyun - OCNDMA with four bidirectional channels 27*4882a593Smuzhiyun - SysDMA with sixteen bidirectional channels 28*4882a593Smuzhiyun - Interfaces 29*4882a593Smuzhiyun - Four-lane SerDes PHY 30*4882a593Smuzhiyun - PCI Express controller complies with the PEX Specification-Rev 2.0 31*4882a593Smuzhiyun - Two Common Public Radio Interface (CPRI) controller lanes 32*4882a593Smuzhiyun - High-speed USB 2.0 host and device controller with ULPI interface 33*4882a593Smuzhiyun - Enhanced secure digital (SD/MMC) host controller (eSDHC) 34*4882a593Smuzhiyun - Antenna interface controller (AIC), supporting four industry 35*4882a593Smuzhiyun standard JESD207/four custom ADI RF interfaces 36*4882a593Smuzhiyun - ADI lanes support both full duplex FDD support & half duplex TDD 37*4882a593Smuzhiyun - Universal Subscriber Identity Module (USIM) interface that 38*4882a593Smuzhiyun facilitates communication to SIM cards or Eurochip pre-paid phone 39*4882a593Smuzhiyun cards 40*4882a593Smuzhiyun - Two DUART, two eSPI, and two I2C controllers 41*4882a593Smuzhiyun - Integrated Flash memory controller (IFC) 42*4882a593Smuzhiyun - GPIO 43*4882a593Smuzhiyun - Sixteen 32-bit timers 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunThe SC3850 core subsystem consists of the following: 46*4882a593Smuzhiyun - 32 KB, 8-way, level 1 instruction cache (L1 ICache) 47*4882a593Smuzhiyun - 32 KB, 8-way, level 1 data cache (L1 DCache) 48*4882a593Smuzhiyun - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory) 49*4882a593Smuzhiyun - Memory management unit (MMU) 50*4882a593Smuzhiyun - Global interrupt controller ( GIC) 51*4882a593Smuzhiyun - Debug and profiling unit (DPU) 52*4882a593Smuzhiyun - Two 32-bit quad timers 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunBSC9132QDS board Overview 55*4882a593Smuzhiyun------------------------- 56*4882a593Smuzhiyun 2Gbyte DDR3 (on board DDR), Dual Ranki 57*4882a593Smuzhiyun 32Mbyte 16bit NOR flash 58*4882a593Smuzhiyun 128Mbyte 2K page size NAND Flash 59*4882a593Smuzhiyun 256 Kbit M24256 I2C EEPROM 60*4882a593Smuzhiyun 128 Mbit SPI Flash memory 61*4882a593Smuzhiyun SD slot 62*4882a593Smuzhiyun USB-ULPI 63*4882a593Smuzhiyun eTSEC1: Connected to SGMII PHY 64*4882a593Smuzhiyun eTSEC2: Connected to SGMII PHY 65*4882a593Smuzhiyun PCIe 66*4882a593Smuzhiyun CPRI 67*4882a593Smuzhiyun SerDes 68*4882a593Smuzhiyun I2C RTC 69*4882a593Smuzhiyun DUART interface: supports one UARTs up to 115200 bps for console display 70*4882a593Smuzhiyun 71*4882a593SmuzhiyunFrequency Combinations Supported 72*4882a593Smuzhiyun-------------------------------- 73*4882a593SmuzhiyunCore MHz/CCB MHz/DDR(MT/s) 74*4882a593Smuzhiyun1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz 75*4882a593Smuzhiyun (SYSCLK = 100MHz, DDRCLK = 100MHz) 76*4882a593Smuzhiyun2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz 77*4882a593Smuzhiyun (SYSCLK = 100MHz, DDRCLK = 133MHz) 78*4882a593Smuzhiyun 79*4882a593SmuzhiyunBoot Methods Supported 80*4882a593Smuzhiyun----------------------- 81*4882a593Smuzhiyun1. NOR Flash 82*4882a593Smuzhiyun2. NAND Flash 83*4882a593Smuzhiyun3. SD Card 84*4882a593Smuzhiyun4. SPI flash 85*4882a593Smuzhiyun 86*4882a593SmuzhiyunDefault Boot Method 87*4882a593Smuzhiyun-------------------- 88*4882a593SmuzhiyunNOR boot 89*4882a593Smuzhiyun 90*4882a593SmuzhiyunBuilding U-Boot 91*4882a593Smuzhiyun-------------- 92*4882a593SmuzhiyunTo build the U-Boot for BSC9132QDS: 93*4882a593Smuzhiyun1. NOR Flash 94*4882a593Smuzhiyun make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK 95*4882a593Smuzhiyun make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK 96*4882a593Smuzhiyun2. NAND Flash : It is currently not supported 97*4882a593Smuzhiyun3. SPI Flash 98*4882a593Smuzhiyun make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK 99*4882a593Smuzhiyun make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK 100*4882a593Smuzhiyun4. SD Card 101*4882a593Smuzhiyun make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK 102*4882a593Smuzhiyun make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK 103*4882a593Smuzhiyun 104*4882a593SmuzhiyunMemory map 105*4882a593Smuzhiyun----------- 106*4882a593Smuzhiyun 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable 107*4882a593Smuzhiyun 0x8000_0000 0x8FFF_FFFF NOR Flash 256M 108*4882a593Smuzhiyun 0x9000_0000 0x9FFF_FFFF PCIe Memory 256M 109*4882a593Smuzhiyun 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M 110*4882a593Smuzhiyun 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M 111*4882a593Smuzhiyun 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M 112*4882a593Smuzhiyun 0xC000_0000 0xC000_7FFF M3 Memory 32K 113*4882a593Smuzhiyun 0xC001_0000 0xC001_FFFF PCI Express I/O 64K 114*4882a593Smuzhiyun 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M 115*4882a593Smuzhiyun 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K 116*4882a593Smuzhiyun 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K 117*4882a593Smuzhiyun 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K 118*4882a593Smuzhiyun 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K 119*4882a593Smuzhiyun 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M 120*4882a593Smuzhiyun 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M 121*4882a593Smuzhiyun 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M 122*4882a593Smuzhiyun 123*4882a593SmuzhiyunFlashing Images 124*4882a593Smuzhiyun--------------- 125*4882a593SmuzhiyunTo place a new U-Boot image in the NAND flash and then boot 126*4882a593Smuzhiyunwith that new image temporarily, use this: 127*4882a593Smuzhiyun tftp 1000000 u-boot-nand.bin 128*4882a593Smuzhiyun nand erase 0 100000 129*4882a593Smuzhiyun nand write 1000000 0 100000 130*4882a593Smuzhiyun reset 131*4882a593Smuzhiyun 132*4882a593SmuzhiyunUsing the Device Tree Source File 133*4882a593Smuzhiyun--------------------------------- 134*4882a593SmuzhiyunTo create the DTB (Device Tree Binary) image file, 135*4882a593Smuzhiyunuse a command similar to this: 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb 138*4882a593Smuzhiyun 139*4882a593SmuzhiyunLikely, that .dts file will come from here; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts 142*4882a593Smuzhiyun 143*4882a593SmuzhiyunBooting Linux 144*4882a593Smuzhiyun------------- 145*4882a593SmuzhiyunPlace a linux uImage in the TFTP disk area. 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun tftp 1000000 uImage 148*4882a593Smuzhiyun tftp 2000000 rootfs.ext2.gz.uboot 149*4882a593Smuzhiyun tftp c00000 bsc9132qds.dtb 150*4882a593Smuzhiyun bootm 1000000 2000000 c00000 151