1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * Author: Shaveta Leekha <shaveta@freescale.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __IDT8T49N222A_SERDES_CLK_H_ 9*4882a593Smuzhiyun #define __IDT8T49N222A_SERDES_CLK_H_ 1 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun #include <i2c.h> 13*4882a593Smuzhiyun #include "qixis.h" 14*4882a593Smuzhiyun #include "../b4860qds/b4860qds_qixis.h" 15*4882a593Smuzhiyun #include <errno.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define NUM_IDT_REGS 23 18*4882a593Smuzhiyun #define NUM_IDT_REGS_FEEDBACK 12 19*4882a593Smuzhiyun #define NUM_IDT_REGS_156_25 11 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* CLK */ 22*4882a593Smuzhiyun enum serdes_refclk { 23*4882a593Smuzhiyun SERDES_REFCLK_100, /* refclk 100Mhz */ 24*4882a593Smuzhiyun SERDES_REFCLK_122_88, /* refclk 122.88Mhz */ 25*4882a593Smuzhiyun SERDES_REFCLK_125, /* refclk 125Mhz */ 26*4882a593Smuzhiyun SERDES_REFCLK_156_25, /* refclk 156.25Mhz */ 27*4882a593Smuzhiyun SERDES_REFCLK_NONE = -1, 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* configuration values for IDT registers for Output Refclks: 31*4882a593Smuzhiyun * Refclk1 = 122.88MHz Refclk2 = 122.88MHz 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00}, 34*4882a593Smuzhiyun {0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00}, 35*4882a593Smuzhiyun {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00}, 36*4882a593Smuzhiyun {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00}, 37*4882a593Smuzhiyun {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12}, 38*4882a593Smuzhiyun {0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08}, 39*4882a593Smuzhiyun {0x16, 0xA0} }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* configuration values for IDT registers for Output Refclks: 43*4882a593Smuzhiyun * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00}, 46*4882a593Smuzhiyun {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00}, 47*4882a593Smuzhiyun {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00}, 48*4882a593Smuzhiyun {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00}, 49*4882a593Smuzhiyun {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14}, 50*4882a593Smuzhiyun {0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08}, 51*4882a593Smuzhiyun {0x16, 0xA0} }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Reconfiguration values for some of IDT registers for 54*4882a593Smuzhiyun * Output Refclks: 55*4882a593Smuzhiyun * Refclk1 = 122.88MHz Refclk2 = 122.88MHz 56*4882a593Smuzhiyun * and with feedback as 1 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7}, 59*4882a593Smuzhiyun {0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07}, 60*4882a593Smuzhiyun {0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B}, 61*4882a593Smuzhiyun {0x14, 0x00}, {0x15, 0xE8} }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* configuration values for IDT registers for Output Refclks: 64*4882a593Smuzhiyun * Refclk1 : 156.25MHz Refclk2 : 156.25MHz 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 67*4882a593Smuzhiyun {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 68*4882a593Smuzhiyun {0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, 69*4882a593Smuzhiyun {0x15, 0xE8} }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* configuration values for IDT registers for Output Refclks: 72*4882a593Smuzhiyun * Refclk1 : 100MHz Refclk2 : 156.25MHz 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 75*4882a593Smuzhiyun {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 76*4882a593Smuzhiyun {0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, 77*4882a593Smuzhiyun {0x15, 0xE8} }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* configuration values for IDT registers for Output Refclks: 80*4882a593Smuzhiyun * Refclk1 : 125MHz Refclk2 : 156.25MHz 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 83*4882a593Smuzhiyun {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 84*4882a593Smuzhiyun {0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, 85*4882a593Smuzhiyun {0x15, 0xE8} }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* configuration values for IDT registers for Output Refclks: 88*4882a593Smuzhiyun * Refclk1 : 156.25MHz Refclk2 : 100MHz 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 91*4882a593Smuzhiyun {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 92*4882a593Smuzhiyun {0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C}, 93*4882a593Smuzhiyun {0x15, 0xE8} }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* configuration values for IDT registers for Output Refclks: 96*4882a593Smuzhiyun * Refclk1 : 156.25MHz Refclk2 : 125MHz 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03}, 99*4882a593Smuzhiyun {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, 100*4882a593Smuzhiyun {0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C}, 101*4882a593Smuzhiyun {0x15, 0xE8} }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun int set_serdes_refclk(u8 idt_addr, u8 serdes_num, 104*4882a593Smuzhiyun enum serdes_refclk refclk1, 105*4882a593Smuzhiyun enum serdes_refclk refclk2, u8 feedback); 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #endif /*__IDT8T49N222A_SERDES_CLK_H_ */ 108