Lines Matching +full:2 +full:mhz
26 RK3588_PLL_RATE(1500000000, 2, 250, 1, 0),
27 RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
28 RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
29 RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
30 RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
31 RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
32 RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
33 RK3588_PLL_RATE(850000000, 3, 425, 2, 0),
34 RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
35 RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
36 RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
37 RK3588_PLL_RATE(742500000, 4, 495, 2, 0),
38 RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
39 RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
40 RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
62 RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates),
161 rate = 702 * MHz; in rk3588_center_get_clk()
163 rate = 396 * MHz; in rk3588_center_get_clk()
165 rate = 200 * MHz; in rk3588_center_get_clk()
174 rate = 500 * MHz; in rk3588_center_get_clk()
176 rate = 250 * MHz; in rk3588_center_get_clk()
178 rate = 100 * MHz; in rk3588_center_get_clk()
187 rate = 396 * MHz; in rk3588_center_get_clk()
189 rate = 200 * MHz; in rk3588_center_get_clk()
191 rate = 100 * MHz; in rk3588_center_get_clk()
200 rate = 200 * MHz; in rk3588_center_get_clk()
202 rate = 100 * MHz; in rk3588_center_get_clk()
204 rate = 50 * MHz; in rk3588_center_get_clk()
223 if (rate >= 700 * MHz) in rk3588_center_set_clk()
225 else if (rate >= 396 * MHz) in rk3588_center_set_clk()
227 else if (rate >= 200 * MHz) in rk3588_center_set_clk()
236 if (rate >= 500 * MHz) in rk3588_center_set_clk()
238 else if (rate >= 250 * MHz) in rk3588_center_set_clk()
240 else if (rate >= 99 * MHz) in rk3588_center_set_clk()
249 if (rate >= 396 * MHz) in rk3588_center_set_clk()
251 else if (rate >= 198 * MHz) in rk3588_center_set_clk()
253 else if (rate >= 99 * MHz) in rk3588_center_set_clk()
262 if (rate >= 198 * MHz) in rk3588_center_set_clk()
264 else if (rate >= 99 * MHz) in rk3588_center_set_clk()
266 else if (rate >= 50 * MHz) in rk3588_center_set_clk()
314 rate = 100 * MHz; in rk3588_top_get_clk()
316 rate = 50 * MHz; in rk3588_top_get_clk()
361 if (rate == 100 * MHz) in rk3588_top_set_clk()
363 else if (rate == 50 * MHz) in rk3588_top_set_clk()
426 rate = 200 * MHz; in rk3588_i2c_get_clk()
428 rate = 100 * MHz; in rk3588_i2c_get_clk()
439 if (rate >= 198 * MHz) in rk3588_i2c_set_clk()
517 return 200 * MHz; in rk3588_spi_get_clk()
519 return 150 * MHz; in rk3588_spi_get_clk()
533 if (rate >= 198 * MHz) in rk3588_spi_set_clk()
535 else if (rate >= 140 * MHz) in rk3588_spi_set_clk()
592 con = readl(&cru->pmuclksel_con[2]); in rk3588_pwm_get_clk()
601 return 100 * MHz; in rk3588_pwm_get_clk()
603 return 50 * MHz; in rk3588_pwm_get_clk()
617 if (rate >= 99 * MHz) in rk3588_pwm_set_clk()
619 else if (rate >= 50 * MHz) in rk3588_pwm_set_clk()
641 rk_clrsetreg(&cru->pmuclksel_con[2], in rk3588_pwm_set_clk()
677 prate = 100 * MHz; in rk3588_adc_get_clk()
801 prate = 702 * MHz; in rk3588_mmc_get_clk()
841 if (!(702 * MHz % rate)) { in rk3588_mmc_set_clk()
843 div = DIV_ROUND_UP(702 * MHz, rate); in rk3588_mmc_set_clk()
966 parent = 702 * MHz; in rk3588_aclk_vop_get_clk()
973 return 396 * MHz; in rk3588_aclk_vop_get_clk()
975 return 200 * MHz; in rk3588_aclk_vop_get_clk()
977 return 100 * MHz; in rk3588_aclk_vop_get_clk()
984 return 200 * MHz; in rk3588_aclk_vop_get_clk()
986 return 100 * MHz; in rk3588_aclk_vop_get_clk()
988 return 50 * MHz; in rk3588_aclk_vop_get_clk()
1005 if (rate >= 850 * MHz) { in rk3588_aclk_vop_set_clk()
1008 } else if (rate >= 750 * MHz) { in rk3588_aclk_vop_set_clk()
1010 div = 2; in rk3588_aclk_vop_set_clk()
1011 } else if (rate >= 700 * MHz) { in rk3588_aclk_vop_set_clk()
1028 if (rate == 400 * MHz || rate == 396 * MHz) in rk3588_aclk_vop_set_clk()
1030 else if (rate == 200 * MHz) in rk3588_aclk_vop_set_clk()
1032 else if (rate == 100 * MHz) in rk3588_aclk_vop_set_clk()
1041 if (rate == 200 * MHz) in rk3588_aclk_vop_set_clk()
1043 else if (rate == 100 * MHz) in rk3588_aclk_vop_set_clk()
1045 else if (rate == 50 * MHz) in rk3588_aclk_vop_set_clk()
1325 con = readl(&cru->clksel_con[reg + 2]); in rk3588_uart_get_rate()
1367 div = 2; in rk3588_uart_set_rate()
1371 div = 2; in rk3588_uart_set_rate()
1414 rk_clrsetreg(&cru->clksel_con[reg + 2], in rk3588_uart_set_rate()
1807 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
1932 sel = 2; in rk3588_dclk_vop_set_parent()
1961 sel = 2; in rk3588_dclk_vop_set_parent()
1971 sel = 2; in rk3588_dclk_vop_set_parent()
1981 sel = 2; in rk3588_dclk_vop_set_parent()
2026 div = DIV_ROUND_UP(GPLL_HZ, 300 * MHz); in rk3588_clk_init()
2216 return 702 * MHz; in rk3588_clk_scmi_get_rate()
2226 else if (src == 2) in rk3588_clk_scmi_get_rate()
2241 return 175 * MHz; in rk3588_clk_scmi_get_rate()
2243 return 116 * MHz; in rk3588_clk_scmi_get_rate()
2244 else if (src == 2) in rk3588_clk_scmi_get_rate()
2245 return 58 * MHz; in rk3588_clk_scmi_get_rate()
2252 return 350 * MHz; in rk3588_clk_scmi_get_rate()
2254 return 233 * MHz; in rk3588_clk_scmi_get_rate()
2255 else if (src == 2) in rk3588_clk_scmi_get_rate()
2256 return 116 * MHz; in rk3588_clk_scmi_get_rate()
2263 return 350 * MHz; in rk3588_clk_scmi_get_rate()
2265 return 233 * MHz; in rk3588_clk_scmi_get_rate()
2266 else if (src == 2) in rk3588_clk_scmi_get_rate()
2267 return 116 * MHz; in rk3588_clk_scmi_get_rate()
2271 src = readl(SCRU_BASE + RK3588_CLKSEL_CON(2)) & 0x00c0; in rk3588_clk_scmi_get_rate()
2274 return 350 * MHz; in rk3588_clk_scmi_get_rate()
2276 return 233 * MHz; in rk3588_clk_scmi_get_rate()
2277 else if (src == 2) in rk3588_clk_scmi_get_rate()
2278 return 116 * MHz; in rk3588_clk_scmi_get_rate()
2282 src = readl(SCRU_BASE + RK3588_CLKSEL_CON(2)) & 0x0300; in rk3588_clk_scmi_get_rate()
2285 return 175 * MHz; in rk3588_clk_scmi_get_rate()
2287 return 116 * MHz; in rk3588_clk_scmi_get_rate()
2288 else if (src == 2) in rk3588_clk_scmi_get_rate()
2289 return 58 * MHz; in rk3588_clk_scmi_get_rate()
2297 src = src >> 2; in rk3588_clk_scmi_get_rate()
2299 return 150 * MHz; in rk3588_clk_scmi_get_rate()
2301 return 100 * MHz; in rk3588_clk_scmi_get_rate()
2302 else if (src == 2) in rk3588_clk_scmi_get_rate()
2303 return 50 * MHz; in rk3588_clk_scmi_get_rate()
2318 writel(BITS_WITH_WMASK(2, 0x7U, 6), in rk3588_clk_scmi_set_rate()
2326 if (rate >= 700 * MHz) in rk3588_clk_scmi_set_rate()
2332 writel(BITS_WITH_WMASK(2, 0x7U, 6), in rk3588_clk_scmi_set_rate()
2341 BITS_WITH_WMASK(2U, 0x3U, 12), in rk3588_clk_scmi_set_rate()
2369 if (rate >= 175 * MHz) in rk3588_clk_scmi_set_rate()
2371 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2373 else if (rate >= 58 * MHz) in rk3588_clk_scmi_set_rate()
2374 src = 2; in rk3588_clk_scmi_set_rate()
2382 if (rate >= 350 * MHz) in rk3588_clk_scmi_set_rate()
2384 else if (rate >= 233 * MHz) in rk3588_clk_scmi_set_rate()
2386 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2387 src = 2; in rk3588_clk_scmi_set_rate()
2395 if (rate >= 350 * MHz) in rk3588_clk_scmi_set_rate()
2397 else if (rate >= 233 * MHz) in rk3588_clk_scmi_set_rate()
2399 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2400 src = 2; in rk3588_clk_scmi_set_rate()
2408 if (rate >= 350 * MHz) in rk3588_clk_scmi_set_rate()
2410 else if (rate >= 233 * MHz) in rk3588_clk_scmi_set_rate()
2412 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2413 src = 2; in rk3588_clk_scmi_set_rate()
2418 SCRU_BASE + RK3588_CLKSEL_CON(2)); in rk3588_clk_scmi_set_rate()
2421 if (rate >= 175 * MHz) in rk3588_clk_scmi_set_rate()
2423 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2425 else if (rate >= 58 * MHz) in rk3588_clk_scmi_set_rate()
2426 src = 2; in rk3588_clk_scmi_set_rate()
2431 SCRU_BASE + RK3588_CLKSEL_CON(2)); in rk3588_clk_scmi_set_rate()
2437 if (rate >= 150 * MHz) in rk3588_clk_scmi_set_rate()
2439 else if (rate >= 100 * MHz) in rk3588_clk_scmi_set_rate()
2441 else if (rate >= 50 * MHz) in rk3588_clk_scmi_set_rate()
2442 src = 2; in rk3588_clk_scmi_set_rate()
2445 writel(BITS_WITH_WMASK(src, 0x3U, 2), in rk3588_clk_scmi_set_rate()