43 #elif (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 2)
115 	/* DPLL VPLL0 VPLL1 mode in 24MHz*/  in rkdclk_init()
131 	/* set vpll1 in 903.168MHz vco = 1.806GHz */  in rkdclk_init()
132 	rk3308_pll_div.refdiv = 2;  in rkdclk_init()
134 	rk3308_pll_div.postdiv1 = 2;  in rkdclk_init()
141 		/* set vpll0 in 786.432MHz vco = 3.146GHz */  in rkdclk_init()
142 		rk3308_pll_div.refdiv = 2;  in rkdclk_init()
149 		/* set vpll0 in 1179.648MHz, vco = 2.359GHz*/  in rkdclk_init()
150 		rk3308_pll_div.refdiv = 2;  in rkdclk_init()
152 		rk3308_pll_div.postdiv1 = 2;  in rkdclk_init()
166 		ddr_pll_sel = 2;  in rkdclk_init()
175 		ddr_pll_sel = 2;  in rkdclk_init()
183 	/* dpll default set in 1300MHz */  in rkdclk_init()
185 		/* set dpll in 1584 MHz ,vco=3.168G*/  in rkdclk_init()
188 		rk3308_pll_div.postdiv1 = 2;  in rkdclk_init()
210 	/* set aclk_bus 216.7MHz */  in rkdclk_init()
215 	/* set pclk_bus 50MHz,hclk_bus 92.857MHz */  in rkdclk_init()
220 	/* set crypto 92.857MHz,crypto_apk 92.857MHz */  in rkdclk_init()
228 	/* set aclk_peri 216.7MHz */  in rkdclk_init()
233 	/* set hclk_peri 92.857MHz,pclk_peri 46.428MHz */  in rkdclk_init()
238 	/* set NANDC 92.857MHz */  in rkdclk_init()
244 	/* set SDMMC 46.4/(internal freq_div 2)=23.2MHz */  in rkdclk_init()
250 	/* set emmc 46.4/(internal freq_div 2)=23.2MHz */  in rkdclk_init()
256 	/* set SFC 24.07/(internal freq_div 2)=12.0MHz */  in rkdclk_init()
263 	rk3308_pll_div.refdiv = 2;  in rkdclk_init()
269 	/* set dpll in 1200 MHz */  in rkdclk_init()
272 	/* set aclk_bus 200MHz */  in rkdclk_init()
277 	/* set pclk_bus 46.15MHz,hclk_bus 100MHz */  in rkdclk_init()
282 	/* set crypto,crypto_apk 100MHz */  in rkdclk_init()
290 	/* set aclk_peri 200MHz */  in rkdclk_init()
295 	/* set hclk_peri 100MHz,pclk_peri 50MHz */  in rkdclk_init()
300 	/* set NANDC 100MHz */  in rkdclk_init()
306 	/* set SDMMC 50MHz */  in rkdclk_init()
312 	/* set emmc 50MHz */  in rkdclk_init()
318 	/* set SFC 24MHz */  in rkdclk_init()
328 	rk3308_pll_div.postdiv1 = 2;  in rkdclk_init()
332 	/* set dpll in 748 MHz */  in rkdclk_init()
335 	/* set aclk_bus 187MHz */  in rkdclk_init()
340 	/* set pclk_bus 46.75MHz,hclk_bus 93.5MHz */  in rkdclk_init()
345 	/* set crypto,crypto_apk 93.5MHz */  in rkdclk_init()
353 	/* set aclk_peri 187MHz */  in rkdclk_init()
358 	/* set hclk_peri 93.5MHz,pclk_peri 46.75MHz */  in rkdclk_init()
363 	/* set NANDC 93.5MHz */  in rkdclk_init()
370 	/* set NANDC 46.75MHz */  in rkdclk_init()
376 	/* set emmc 46.75MHz */  in rkdclk_init()
382 	/* set SFC 23.375MHz */  in rkdclk_init()
389 	/* set spdif tx lower than 100Mhz */  in rkdclk_init()
397 	/* set uart0~4 lower than 100Mhz */  in rkdclk_init()
406 		     uart_div[2] << CLK_UART2_DIV_CON_SHIFT);  in rkdclk_init()
482 			i = 2;  in ddr_msch_cfg_rbc()
486 	} else if (params_priv->ddr_config_t.bank == 2) {  in ddr_msch_cfg_rbc()
566 	writel(2, &priv->service_msch->ddrconf);  in ddr_msch_get_max_col()
632 		else if (UART_INFO_ID(uart_info) == 2)  in ddr_set_atags()
664 	t_serial.id = 2;  in ddr_set_atags()
738 		if (tmp < 2)  in modify_sdram_params()
739 			tmp = 2;  in modify_sdram_params()
750 	u32 gate[2];  in check_rd_gate()
795 	for (dqs = 0; dqs < 2; dqs++) {  in modify_data_training()
815 		writel((max_value + min_value + 1) / 2,  in modify_data_training()