Lines Matching +full:2 +full:mhz

23 	SERDES_REFCLK_100,	/* refclk 100Mhz */
24 	SERDES_REFCLK_122_88,	/* refclk 122.88Mhz */
25 	SERDES_REFCLK_125,	/* refclk 125Mhz */
26 	SERDES_REFCLK_156_25,	/* refclk 156.25Mhz */
31  * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
33 static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
43  * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
45 static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
55  * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
58 static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
64  * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
66 static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
72  * Refclk1 : 100MHz Refclk2 : 156.25MHz
74 static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
80  * Refclk1 : 125MHz Refclk2 : 156.25MHz
82 static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
88  * Refclk1 : 156.25MHz Refclk2 : 100MHz
90 static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03},
96  * Refclk1 : 156.25MHz Refclk2 : 125MHz
98 static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03},