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/OK3568_Linux_fs/kernel/fs/cifs/
H A Dnterr.h26 #define NT_STATUS_MORE_ENTRIES 0x0105
27 #define NT_ERROR_INVALID_PARAMETER 0x0057
28 #define NT_ERROR_INSUFFICIENT_BUFFER 0x007a
29 #define NT_STATUS_1804 0x070c
30 #define NT_STATUS_NOTIFY_ENUM_DIR 0x010c
37 #define NT_STATUS_OK 0x0000
38 #define NT_STATUS_SOME_UNMAPPED 0x0107
39 #define NT_STATUS_BUFFER_OVERFLOW 0x80000005
40 #define NT_STATUS_NO_MORE_ENTRIES 0x8000001a
41 #define NT_STATUS_MEDIA_CHANGED 0x8000001c
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dp1010rdb_36b.dtsi41 ranges = <0x0 0x0 0xf 0xee000000 0x02000000
42 0x1 0x0 0xf 0xff800000 0x00010000
43 0x3 0x0 0xf 0xffb00000 0x00000020>;
44 reg = <0xf 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0xf 0xffe00000 0x100000>;
52 reg = <0xf 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xc0000000
[all …]
H A Dmpc8572ds.dts19 reg = <0 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
22 0x1 0x0 0x0 0xe0000000 0x08000000
23 0x2 0x0 0x0 0xffa00000 0x00040000
24 0x3 0x0 0x0 0xffdf0000 0x00008000
25 0x4 0x0 0x0 0xffa40000 0x00040000
26 0x5 0x0 0x0 0xffa80000 0x00040000
27 0x6 0x0 0x0 0xffac0000 0x00040000>;
31 ranges = <0x0 0 0xffe00000 0x100000>;
35 reg = <0 0xffe08000 0 0x1000>;
[all …]
H A Dp2020ds.dts19 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
20 0x1 0x0 0x0 0xe0000000 0x08000000
21 0x2 0x0 0x0 0xffa00000 0x00040000
22 0x3 0x0 0x0 0xffdf0000 0x00008000
23 0x4 0x0 0x0 0xffa40000 0x00040000
24 0x5 0x0 0x0 0xffa80000 0x00040000
25 0x6 0x0 0x0 0xffac0000 0x00040000>;
26 reg = <0 0xffe05000 0 0x1000>;
30 ranges = <0x0 0x0 0xffe00000 0x100000>;
34 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
[all …]
H A Dp1020rdb_36b.dts18 reg = <0xf 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
22 0x1 0x0 0xf 0xffa00000 0x00040000
23 0x2 0x0 0xf 0xffb00000 0x00020000>;
27 ranges = <0x0 0xf 0xffe00000 0x100000>;
31 reg = <0xf 0xffe09000 0 0x1000>;
32 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
33 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
34 pcie@0 {
35 ranges = <0x2000000 0x0 0xc0000000
[all …]
H A Dp1021rdb-pc_36b.dts45 reg = <0xf 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
49 0x1 0x0 0xf 0xff800000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00020000>;
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
58 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
59 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
60 reg = <0xf 0xffe09000 0 0x1000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
[all …]
H A Dp1020rdb-pc_36b.dts45 reg = <0xf 0xffe05000 0 0x1000>;
48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
49 0x1 0x0 0xf 0xff800000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00040000
51 0x3 0x0 0xf 0xffa00000 0x00020000>;
55 ranges = <0x0 0xf 0xffe00000 0x100000>;
59 reg = <0xf 0xffe09000 0 0x1000>;
60 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
61 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
62 pcie@0 {
[all …]
H A Dge_imp3a.dts22 reg = <0 0xfef05000 0 0x1000>;
24 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
25 0x1 0x0 0x0 0xe0000000 0x08000000
26 0x2 0x0 0x0 0xe8000000 0x08000000
27 0x3 0x0 0x0 0xfc100000 0x00020000
28 0x4 0x0 0x0 0xfc000000 0x00008000
29 0x5 0x0 0x0 0xfc008000 0x00008000
30 0x6 0x0 0x0 0xfee00000 0x00040000
31 0x7 0x0 0x0 0xfee80000 0x00040000>;
33 /* nor@0,0 is a mirror of part of the memory in nor@1,0
[all …]
H A Dmvme2500.dts29 ranges = <0x0 0 0xffe00000 0x100000>;
34 reg = <0x4c>;
39 reg = <0x68>;
40 interrupts = <8 1 0 0>;
45 reg = <0x54>;
50 reg = <0x52>;
55 reg = <0x53>;
60 reg = <0x50>;
68 flash@0 {
70 reg = <0>;
[all …]
H A Dgef_sbc310.dts25 reg = <0x0 0x40000000>; // set by uboot
29 reg = <0xfef05000 0x1000>;
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe0000000 0x08000000 // Paged Flash 0
33 2 0 0xe8000000 0x08000000 // Paged Flash 1
34 3 0 0xfc100000 0x00020000 // NVRAM
35 4 0 0xfc000000 0x00010000>; // FPGA
37 /* flash@0,0 is a mirror of part of the memory in flash@1,0
38 flash@0,0 {
40 reg = <0x0 0x0 0x01000000>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/
H A Ddram_init.c29 .sparse_ch1_base = 0xc0000000,
33 .sparse_ch1_base = 0xa0000000,
37 .sparse_ch1_base = 0xc0000000,
41 .sparse_ch1_base = 0xc0000000,
45 .sparse_ch1_base = 0xc0000000,
50 .sparse_ch1_base = 0xc0000000,
55 .sparse_ch1_base = 0xc0000000,
59 .sparse_ch1_base = 0xc0000000,
64 .sparse_ch1_base = 0xc0000000,
90 dram_map[0].base = CONFIG_SYS_SDRAM_BASE; in uniphier_memconf_decode()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv50.c35 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv50_gr_units()
48 if (ret == 0) { in nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv50_gr_object_bind()
52 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv50_gr_object_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv50_gr_object_bind()
75 if (ret == 0) { in nv50_gr_chan_bind()
100 return 0; in nv50_gr_chan_new()
108 { 0x01, "STACK_UNDERFLOW" },
109 { 0x02, "STACK_MISMATCH" },
[all …]
H A Dgf100.c53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); in gf100_gr_zbc_clear_color()
54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); in gf100_gr_zbc_clear_color()
55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); in gf100_gr_zbc_clear_color()
56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); in gf100_gr_zbc_clear_color()
58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); in gf100_gr_zbc_clear_color()
59 nvkm_wr32(device, 0x405820, zbc); in gf100_gr_zbc_clear_color()
60 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ in gf100_gr_zbc_clear_color()
84 zbc = (zbc < 0) ? i : zbc; in gf100_gr_zbc_color_get()
88 if (zbc < 0) in gf100_gr_zbc_color_get()
104 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); in gf100_gr_zbc_clear_depth()
[all …]
/OK3568_Linux_fs/buildroot/board/stmicroelectronics/stm32f469-disco/patches/linux/
H A D0001-Use-default-dram-address-without-remapping.patch22 - reg = <0x00000000 0x1000000>;
23 + reg = <0xc0000000 0x1000000>;
31 - dma-ranges = <0xc0000000 0x0 0x10000000>;
32 + dma-ranges = <0xc0000000 0xc0000000 0x10000000>;
37 2.32.0
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/bus/
H A Darm,integrator-ap-lm.yaml15 determine if a logic module is connected at index 0, 1, 2 or 3. The logic
35 "^bus(@[0-9a-f]*)?$":
37 and are named with bus. The first module is at 0xc0000000, the second
38 at 0xd0000000 and so on until the top of the memory of the system at
39 0xffffffff. All information about the memory used by the module is
55 ranges = <0xc0000000 0xc0000000 0x40000000>;
60 ranges = <0x00000000 0xc0000000 0x10000000>;
61 /* The Logic Modules sees the Core Module 0 RAM @80000000 */
62 dma-ranges = <0x00000000 0x80000000 0x10000000>;
68 reg = <0x00100000 0x1000>;
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_powertune.h26 #define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xfffc0000
27 #define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x12
28 #define DIDT_TD_CTRL0__UNUSED_0_MASK 0xfffc0000
29 #define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x12
30 #define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xfffc0000
31 #define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x12
32 #define DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK 0xc0000000
33 #define DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e
34 #define DIDT_TD_TUNING_CTRL__UNUSED_0_MASK 0xc0000000
35 #define DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx53-tqma53.dtsi15 reg = <0x70000000 0x40000000>; /* Up to 1GiB */
21 #size-cells = <0>;
23 reg_3p3v: regulator@0 {
25 reg = <0>;
36 pinctrl-0 = <&pinctrl_esdhc2>,
46 pinctrl-0 = <&pinctrl_uart3>;
52 pinctrl-0 = <&pinctrl_ecspi1>;
60 pinctrl-0 = <&pinctrl_esdhc3>;
69 pinctrl-0 = <&pinctrl_hog>;
74 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
[all …]
H A Dintegratorap.dts17 #size-cells = <0>;
19 cpu@0 {
28 reg = <0>;
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
[all …]
H A Dimx53-smd.dts16 reg = <0x70000000 0x40000000>;
24 gpios = <&gpio2 14 0>;
30 gpios = <&gpio2 15 0>;
38 pinctrl-0 = <&pinctrl_esdhc1>;
46 pinctrl-0 = <&pinctrl_esdhc2>;
53 pinctrl-0 = <&pinctrl_uart3>;
60 pinctrl-0 = <&pinctrl_ecspi1>;
64 zigbee: mc1323@0 {
67 reg = <0>;
77 partition@0 {
[all …]
H A Dimx53-m53evk.dts17 pinctrl-0 = <&pinctrl_ipu_disp1>;
44 pwms = <&pwm1 0 3000>;
45 brightness-levels = <0 4 8 16 32 64 128 255>;
53 pinctrl-0 = <&led_pin_gpio>;
57 gpios = <&gpio2 8 0>;
63 gpios = <&gpio2 9 0>;
71 #size-cells = <0>;
79 gpio = <&gpio1 2 0>;
88 gpio = <&gpio1 4 0>;
111 pinctrl-0 = <&pinctrl_audmux>;
[all …]
H A Dhip04-d01.dts18 memory@0,10000000 {
20 reg = <0x00000000 0x10000000 0x00000000 0xc0000000>,
21 <0x00000004 0xc0000000 0x00000003 0x40000000>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/socionext/
H A Duniphier-ld20-akebi96.dts43 reg = <0 0x80000000 0 0xc0000000>;
48 reg = <0 0xc0000000 0 0x02000000>;
61 reg = <0 0xc0000000 0 0x02000000>;
75 #sound-dai-cells = <0>;
77 port@0 {
86 #sound-dai-cells = <0>;
88 port@0 {
106 #size-cells = <0>;
107 usb-over-spi@0 {
109 reg = <0>;
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dmpc83xx.h24 #define EXC_OFF_SYS_RESET 0x0100
32 #define CONFIG_DEFAULT_IMMR 0xFF400000
35 #define IMMRBAR 0x0000
36 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
43 #define LBLAWBAR0 0x0020
44 #define LBLAWAR0 0x0024
45 #define LBLAWBAR1 0x0028
46 #define LBLAWAR1 0x002C
47 #define LBLAWBAR2 0x0030
48 #define LBLAWAR2 0x0034
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-bcm283x/
H A Dphys2bus.c13 return 0xc0000000 | phys; in phys_to_bus()
15 return 0x40000000 | phys; in phys_to_bus()
21 return bus & ~0xc0000000; in bus_to_phys()
/OK3568_Linux_fs/u-boot/include/configs/
H A DMPC8544DS.h15 #define CONFIG_SYS_TEXT_BASE 0xfff80000
34 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
47 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
48 #define CONFIG_SYS_MEMTEST_END 0x00400000
50 #define CONFIG_SYS_CCSRBAR 0xe0000000
59 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
61 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
69 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
81 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
83 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
[all …]

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