1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * P1020 RDB Device Tree Source (36-bit address map) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2009-2011 Freescale Semiconductor Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/include/ "p1020si-pre.dtsi" 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "fsl,P1020RDB"; 11*4882a593Smuzhiyun compatible = "fsl,P1020RDB"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun memory { 14*4882a593Smuzhiyun device_type = "memory"; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun board_lbc: lbc: localbus@fffe05000 { 18*4882a593Smuzhiyun reg = <0xf 0xffe05000 0 0x1000>; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ 21*4882a593Smuzhiyun ranges = <0x0 0x0 0xf 0xef000000 0x01000000 22*4882a593Smuzhiyun 0x1 0x0 0xf 0xffa00000 0x00040000 23*4882a593Smuzhiyun 0x2 0x0 0xf 0xffb00000 0x00020000>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun board_soc: soc: soc@fffe00000 { 27*4882a593Smuzhiyun ranges = <0x0 0xf 0xffe00000 0x100000>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun pci0: pcie@fffe09000 { 31*4882a593Smuzhiyun reg = <0xf 0xffe09000 0 0x1000>; 32*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 33*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; 34*4882a593Smuzhiyun pcie@0 { 35*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xc0000000 36*4882a593Smuzhiyun 0x2000000 0x0 0xc0000000 37*4882a593Smuzhiyun 0x0 0x20000000 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun 0x1000000 0x0 0x0 40*4882a593Smuzhiyun 0x1000000 0x0 0x0 41*4882a593Smuzhiyun 0x0 0x100000>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun pci1: pcie@fffe0a000 { 46*4882a593Smuzhiyun reg = <0xf 0xffe0a000 0 0x1000>; 47*4882a593Smuzhiyun ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000 48*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; 49*4882a593Smuzhiyun pcie@0 { 50*4882a593Smuzhiyun ranges = <0x2000000 0x0 0x80000000 51*4882a593Smuzhiyun 0x2000000 0x0 0x80000000 52*4882a593Smuzhiyun 0x0 0x20000000 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun 0x1000000 0x0 0x0 55*4882a593Smuzhiyun 0x1000000 0x0 0x0 56*4882a593Smuzhiyun 0x0 0x100000>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun/include/ "p1020rdb.dtsi" 62*4882a593Smuzhiyun/include/ "p1020si-post.dtsi" 63